System management interrupt source including a programmable counter and power management system employing the same

• US 5,606,713 A
• Filed: 11/06/1995
• Issued: 02/25/1997
• Est. Priority Date: 02/02/1994
• Status: Expired due to Term

• Current Assignee: Advanced Micro Devices, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Wisor, Michael T., O'Brien, Rita M.
• Primary Examiner(s): Pan, Daniel H.
• Application Number:
  US08/554,396
• Time in Patent Office: 477 Days
• Field of Search: 395/182.22, 395/185.08, 395/800, 395/550, 395/750, 395/700, 395/182.2, 364/DIG. 1, 364/483, 364/DIG. 2, 364/492, 364/140, 364/145, 364/464.04, 340/825.08, 340/663, 455/127, 455/117
• US Class Current: 712/40
• CPC Class Codes: G06F 13/24 using interrupt G06F13/32 takes precedence

Abstract

A periodic system management interrupt (SMI) source is provided that includes a programmable timer for asserting an SMI a predetermined rate. A microprocessor is coupled to a periodic SMI source through a CPU local bus. The periodic SMI source may be programmed by executing an I/O write cycle which allows a count value and an enable bit to be loaded into an internal configuration register. When the enable bit is set, the programmable timer asserts a periodic system management interrupt at a fixed rate as determined by the count value within the configuration register. The periodic system management interrupt may be asserted, for example, at intervals of 16 milliseconds, 64 milliseconds, 245 milliseconds, 1 second, 16 seconds, or 1 minute. The periodic SMI source allows for the automatic generation of a periodic system management interrupt independently of software.

Claims

1. A computer system comprising:

a microprocessor including a system management interrupt input terminal and a general purpose interrupt input terminal, wherein said microprocessor is configured to process an interrupt received at said system management interrupt input terminal with a higher priority and with precedence over an interrupt simultaneously received at said general purpose interrupt input terminal;

a system management interrupt source coupled to said system management interrupt input terminal, wherein said system management interrupt source includes;

a programmable counter capable of asserting a system management interrupt signal at a predetermined periodic rate independent of other system activity as long as an enable bit is set;

a configuration register coupled to said programmable counter and capable of receiving a count value indicative of said predetermined periodic rate during an I/O write cycle generated by said microprocessor, wherein said configuration register includes a storage location for storing said enable bit, and wherein an output of said storage location is coupled to said programmable counter whereby said enable bit selectively enables said programmable counter;

a decoder coupled to said configuration register for decoding an address signal during said I/O write cycle and for causing said count value to be stored within said configuration register;

a battery for providing power to said computer system;

a battery monitor coupled to said battery for monitoring an output voltage level of said battery;

an I/O port coupled to said battery monitor for reading a digital value indicative of said output voltage level; and

a power management subsystem associated with said microprocessor, wherein said microprocessor causes said power management subsystem to read said digital value indicative of said output voltage level from said I/O port in response to the assertion of said system management interrupt signal.

2. The computer system as recited in claim 1 wherein said microprocessor is coupled to said system management interrupt source via a CPU local bus.

3. The computer system as recited in claim 1 wherein said power management subsystem is further capable of tracking an estimated capacity value of said battery.

4. The computer system as recited in claim 1 wherein said programmable counter is programmable such that said system management interrupt signal is asserted at intervals ranging from 16 milliseconds to 1 minute.

5. The computer system as recited in claim 1 wherein said decoder further receives an I/O write signal.