Memory circuitry having bus interface for receiving information in packets and access time registers

• US 5,606,717 A
• Filed: 03/05/1992
• Issued: 02/25/1997
• Est. Priority Date: 04/18/1990
• Status: Expired due to Fees

• Current Assignee: Rambus Inc.
• Original Assignee: Rambus Inc.
• Inventors: Horowitz, Mark, Farmwald, Michael
• Primary Examiner(s): Shin, Christopher B.
• Application Number:
  US07/847,651
• Time in Patent Office: 1,818 Days
• Field of Search: 395/275, 395/200, 395/550, 395/284, 395/288, 395/310, 395/287, 395/290, 395/292, 395/299, 395/285, 398/821-867
• US Class Current: 710/36
• CPC Class Codes: G06F 11/006 Identification G06F11/2289 takes precedence
• CPC Class Codes: G06F 11/1048 using arrangements adapted for a specific error detection or correction feature
• CPC Class Codes: G06F 12/0215 with look ahead addressing means
• CPC Class Codes: G06F 12/0661 and decentralised selection
• CPC Class Codes: G06F 12/0684 with feedback, e.g. presence or absence of unit detected by addressing, overflow detection
• CPC Class Codes: G06F 13/1605 based on arbitration arbitration in handling access to a common bus or bus system G06F13/36
• CPC Class Codes: G06F 13/161 with latency improvement
• CPC Class Codes: G06F 13/1678 using bus width
• CPC Class Codes: G06F 13/1689 Synchronisation and timing concerns synchronisation on a memory bus G06F13/4234
• CPC Class Codes: G06F 13/1694 Configuration of memory controller to different memory types
• CPC Class Codes: G06F 13/376 using a contention resolving method, e.g. collision detection, collision avoidance
• CPC Class Codes: G06F 13/4239 with asynchronous protocol
• CPC Class Codes: G11C 11/4076 Timing circuits for regeneration management G11C11/406
• CPC Class Codes: G11C 11/4096 Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
• CPC Class Codes: G11C 2207/105 Aspects related to pads, pins or terminals
• CPC Class Codes: G11C 2207/108 Wide data ports
• CPC Class Codes: G11C 29/88 with partially good memories
• CPC Class Codes: G11C 5/00 Details of stores covered by group G11C11/00
• CPC Class Codes: G11C 5/04 Supports for storage elements , e.g. memory modules; Mounting or fixing of storage elements on such supports
• CPC Class Codes: G11C 5/06 Arrangements for interconnecting storage elements electrically, e.g. by wiring
• CPC Class Codes: G11C 5/063 : Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
• CPC Class Codes: G11C 5/066 : Means for reducing external access-lines for a semiconductor memory clip, e.g. by multiplexing at least address and data signals
• CPC Class Codes: G11C 7/1006 : Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
• CPC Class Codes: G11C 7/1012 : Data reordering during input/output, e.g. crossbars, layers of multiplexers, shifting or rotating
• CPC Class Codes: G11C 7/1045 : Read-write mode select circuits
• CPC Class Codes: G11C 7/1051 : Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
• CPC Class Codes: G11C 7/1057 : Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load
• CPC Class Codes: G11C 7/1066 : Output synchronization
• CPC Class Codes: G11C 7/1069 : I/O lines read out arrangements
• CPC Class Codes: G11C 7/1072 : for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
• CPC Class Codes: G11C 7/1078 : Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
• CPC Class Codes: G11C 7/1084 : Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load
• CPC Class Codes: G11C 7/22 : Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: G11C 7/222 : Clock generating, synchronizing or distributing circuits within memory device
• CPC Class Codes: G11C 7/225 : Clock input buffers
• CPC Class Codes: G11C 8/00 : Arrangements for selecting an address in a digital store for stores using transistors G11C11/407, G11C11/413
• CPC Class Codes: Y02D 10/00 : Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

An interfacing circuitry for a semiconductor circuit of a computer system selects the semiconductor circuit for a device operation in accordance with data, addresses, and control information received from a multiline bus of the computer system in a form of packets. The computer system has a plurality of semiconductor circuits. The interfacing circuitry is coupled to the multiline bus. The multiline bus has a total number of lines less than a total number of bits in any single address. The interfacing circuitry resides inside the semiconductor circuit and includes a decoder for decoding the packets received to identify the data, addresses, and control information. A control logic circuitry is coupled to the decoder circuitry for controlling device operation of the first semiconductor circuit in accordance with the data, addresses, and control information received. A register circuitry is coupled to the decoder and the control logic circuitry for storing a first value corresponding to a first predetermined time period during which the interfacing circuitry must wait before transmitting reply information through the multiline bus in response to the data, addresses, and control information received. The register circuitry applies the first value to the control logic circuitry to cause the control logic circuitry to wait for the first predetermined time period before accessing the multiline bus for transmitting the reply information.

Claims

1. An interface circuitry for accessing a semiconductor memory circuit, comprising:

(A) receiver circuitry coupled to a multiline bus for receiving data, addresses, and control information that are multiplexed and transmitted in a form of packets via the multiline bus, wherein the multiline bus has a total number of lines less than a total number of bits in any single address, wherein the computer system includes a plurality of semiconductor circuits, including the memory circuit, wherein all circuitry of the interfacing circuitry resides inside the memory circuit;

(B) decoder circuitry coupled to the receiver circuitry for decoding the packets received in the receiver circuitry to identify the data, addresses, and control information;

(C) control logic circuitry coupled to the decoder circuitry for controlling device operation of the memory circuit in accordance with the data, addresses, and control information received from the multiline bus and for transmitting reply information through the multiline bus in response to the data, addresses, and control information received, the reply information generated in response to accessing the memory circuit; and

;

(D) register circuitry coupled to the control logic circuitry for storing a first value corresponding to a first predetermined time period during which the interfacing circuitry must wait before transmitting the reply information through the multiline bus, wherein the register circuitry applies the first value to the control logic circuitry to cause the control logic circuitry to wait for the first predetermined time period before accessing the multiline bus for transmitting the reply information, wherein the register circuitry allows modification of the first value by the control logic circuitry under control of the data, addresses, and control information received from the multiline bus.

2. The interfacing circuitry of claim 1, wherein the register circuitry further comprises a first register for storing the first value and a second register for storing a second value corresponding to a second predetermined time period during which the interfacing circuitry must wait before transmitting the reply information through the multiline bus in response to the data, addresses, and control information received.

3. The interfacing circuitry of claim 2, wherein the second value is permanently set in the second register.

4. The interfacing circuitry of claim 3, wherein the control logic circuitry accesses the first register to modify the first value under the control of the data, addresses, and control information received from the multiline bus.

5. The interfacing circuitry of claim 1, wherein the memory circuit is a dynamic random read memory (DRAM).

6. The interfacing circuitry of claim 1, further comprising

(I) device identification register circuitry for storing a device identification value of the memory circuit;

(II) comparator circuitry coupled to the device identification register circuitry and the decoder circuitry for comparing the device identification value with a device select data contained in the control information, wherein the comparator circuitry generates a match signal when the device identification value matches the device select data such that the memory circuit is selected without a separate device selection line, wherein the control logic circuitry is activated to control the device operation of the memory circuit when the comparator circuitry generates the match signal.