Safety optimization in microprocessor controlled implantable devices

• US 5,607,458 A
• Filed: 07/13/1995
• Issued: 03/04/1997
• Est. Priority Date: 07/13/1995
• Status: Expired due to Term

• Current Assignee: Pacesetter Incorporated (Abbott Laboratories Incorporated)
• Original Assignee: Pacesetter Incorporated (Abbott Laboratories Incorporated)
• Inventors: Causey, James D. III, Yang, Min-Yaug
• Primary Examiner(s): Jastrzab, Jeffrey R.
• Application Number:
  US08/501,838
• Time in Patent Office: 600 Days
• Field of Search: 607/4, 607/5, 607/9, 607/11, 607/27, 607/31, 607/63
• US Class Current: 607/27
• CPC Class Codes: A61N 1/37 Monitoring; Protecting
• CPC Class Codes: A61N 1/3718 Monitoring of or protection against external electromagnetic fields or currents
• CPC Class Codes: A61N 1/3931 Protecting, e.g. back-up systems

Abstract

A microprocessor-controlled implantable cardiac stimulating device having a normal mode, an intermediate mode, and a backup pacing mode is provided. The device switches from one mode to another in response to the detection of any one of an address error, parity error, opcode error, or watchdog timer error. The microprocessor is shut down during the delivery of a cardioversion or defibrillation shock in order to prevent signals produced by the microprocessor from being subjected to transient electrical signals. The interrupt registers of the microprocessor are also disabled during the delivery of a cardioversion or defibrillation shock. In an alternative embodiment, an implantable cardiac stimulating device is provided with redundant microprocessors in order to detect malfunctions of the microprocessors.

Claims

1. An implantable cardiac stimulating device comprising:

a microprocessor;

a memory device coupled to the microprocessor;

a pulse delivery circuit, coupled to the microprocessor, for delivering an electrical stimulation pulse to a patient'"'"'s heart;

a backup pacing circuit for delivering backup pacing to the patient'"'"'s heart;

at least one error detection circuit for detecting errors in the implantable cardiac stimulating device; and

switching circuitry, coupled to each of the microprocessor, the at least one error detection circuit, and the backup pacing circuit, for switching the implantable cardiac stimulating device from a normal mode to an intermediate mode in response to a first error detected by the at least one error detection circuit, and for switching the implantable cardiac stimulating device from the intermediate mode to a backup pacing mode in response to a second error detected by the at least one error detection circuit;

wherein;

while the implantable cardiac'"'"'stimulating device is in the normal mode, the pulse delivery circuit is controlled by the microprocessor, and the microprocessor is able to store data in and retrieve data from the memory device;

while the implantable cardiac stimulating device is in the intermediate mode, the pulse delivery circuit is controlled by the microprocessor, the microprocessor is able to store data in the memory device, and the microprocessor is able to retrieve data that have been stored in the memory device after the implantable cardiac stimulating device entered the intermediate mode; and

while the implantable cardiac stimulating device is in the backup pacing mode, the backup pacing circuit is activated.

2. The device of claim 1, further comprising means for disabling the microprocessor is while the implantable cardiac stimulating device is in the backup pacing mode.

3. The device of claim 1, wherein the at least one error detection circuit comprises:

an address decoder for detecting address errors in the device.

4. The device of claim 3, wherein the address decoder decodes an address of a location of the memory device when the microprocessor attempts to access the location in order to determine if the location is a valid location.

5. The device of claim 1, wherein the at least one error detection circuit comprises:

a parity checker for detecting parity errors in the device.

6. The device of claim 5, wherein a plurality of data bytes are stored in the memory device, each of the data bytes comprising a plurality of data bits and a parity bit which indicates the parity of the data bits, and wherein the parity checker compares the parity bit to the parity of the data bits in order to determine if the parity bit is correct.

7. The device of claim 1, wherein the at least one error detection circuit comprises:

an opcode decoder for detecting opcode errors in the device.

8. The device of claim 7, wherein the opcode decoder determines if an opcode which is about to be fetched by the microprocessor is a valid opcode.

9. The device of claim 1, further comprising:

interrupt generating circuitry for generating an interrupt signal which is received by the microprocessor, the microprocessor being able to generate an acknowledgment signal in response to receiving the interrupt signal;

wherein the at least one error detection circuit comprises a watchdog timer circuit; and

wherein when the microprocessor does not communicate a proper acknowledgment signal to the watchdog timer circuit within a predetermined interval of time after the microprocessor receives the interrupt signal, the watchdog timer circuit triggers the switching circuitry to switch the implantable cardiac stimulating device to the backup pacing mode.

10. The device of claim 9, wherein the watchdog timer circuit triggers the switching circuitry to switch the implantable cardiac stimulating device to the backup pacing mode if more than one acknowledgment signal is received by the watchdog timer circuit within a predetermined interval of time.

11. The device of claim 9, wherein the switching circuitry comprises the watchdog timer circuit.

12. The device of claim 9, wherein the watchdog timer circuit triggers the switching circuitry to switch the implantable cardiac stimulating device from the normal mode to the backup pacing mode.

13. The device of claim 9, wherein the watchdog timer circuit triggers the switching circuitry to switch the implantable cardiac stimulating device from the intermediate mode to the backup pacing mode.

14. The device of claim 1, wherein:

the pulse delivery circuit comprises high voltage shocking circuitry coupled to at least one output capacitor; and

the at least one error detection circuit comprises high voltage monitoring means for monitoring a predetermined voltage on the output capacitor.

15. The device of claim 1, wherein:

the pulse delivery circuit comprises high voltage shocking circuitry coupled to at least one output capacitor; and

the at least one error detection circuit comprises high voltage monitoring means for monitoring the amount of shock delivered to the patient.

16. A method of operating an implantable cardiac stimulating device, the implantable cardiac stimulating device including a pulse delivery circuit for delivering electrical stimulation pulses to a patient'"'"'s heart, a microprocessor, a memory device, at least one error detection circuit for detecting errors in the implantable cardiac stimulating device, and a backup pacing circuit for delivering backup pacing to the patient'"'"'s heart, the method comprising the steps of:

providing a normal mode of operation for the implantable cardiac stimulating device in which the pulse delivery circuit is controlled by the microprocessor, wherein the microprocessor is able to store data in and retrieve data from the memory device;

providing an intermediate mode of operation for the implantable cardiac stimulating device in which the pulse delivery circuit is controlled by the microprocessor, the microprocessor is able to store data in the memory device, and the microprocessor is able to retrieve data that have been stored in the memory device after the implantable cardiac stimulating device has entered the intermediate mode;

providing a backup pacing mode of the implantable cardiac stimulating device in which the backup pacing circuitry is activated; and

switching the implantable cardiac stimulating device from the normal mode to the intermediate mode in response to a first error detected by the at least one error detection circuit, and switching the implantable cardiac stimulating device from the intermediate mode to the backup pacing mode in response to a second error detected by the at least one error detection circuit.

17. The method of claim 16, further comprising the step of:

disabling the microprocessor in response to the second at least one error detected by the at least one error detection circuit.

18. The method of claim 16, wherein the switching step further comprises the step of:

switching the implantable cardiac stimulating device in response to an address error detected by the at least one error detection circuit.

19. The method of claim 16, wherein the switching step further comprises the step of:

switching the implantable cardiac stimulating device in response to a parity error detected by the at least one error detection circuit.

20. The method of claim 16, wherein the switching step further comprises the step of:

switching the implantable cardiac stimulating device in response to an opcode error detected by the at least one error detection circuit.

21. The method of claim 16, wherein the at least one error detection circuit comprises a watchdog timer circuit, and wherein the method further comprises the steps of:

providing an interrupt signal to the microprocessor, the microprocessor being able to communicate an acknowledgment signal to the watchdog timer circuit in response to receiving the interrupt signal;

switching the implantable cardiac stimulating device to the backup pacing mode when a proper acknowledgment signal is not received by the watchdog timer circuit from the microprocessor within a predetermined interval of time after the microprocessor receives the interrupt signal.

22. The method of claim 21, further comprising the step of:

switching the implantable cardiac stimulating device to the backup pacing mode if more than one acknowledgment signal is received by the watchdog timer circuit within a predetermined interval of time.