Image cell for an image-recorder chip, for protection of high input signal dynamics onto reduced output signal dynamics

• US 5,608,204 A
• Filed: 06/26/1995
• Issued: 03/04/1997
• Est. Priority Date: 03/24/1992
• Status: Expired due to Term

• Current Assignee: Institut Fur Mikroelektronik Stuttgart
• Original Assignee: Institut Fur Mikroelektronik Stuttgart
• Inventors: Landgraf, Marc, Seger, Ulrich, Hofflinger, Bernd
• Primary Examiner(s): LE, QUE TAN
• Application Number:
  US08/302,826
• Time in Patent Office: 617 Days
• Field of Search: 250/208.1, 250/214 R, 250/214 LA, 250/214.1, 327/514, 327/515, 257/232, 257/233, 257/292-294, 257/443, 257/444, 257/448, 348/308-309, 348/294-297
• US Class Current: 250/208.1
• CPC Class Codes: H01L 27/14609 Pixel-elements with integrated switching, control, storage or amplification elements scanning details of imagers (circuitry of solid-state image sensors H04N25/00); circuitry of imagers H04N25/70
• CPC Class Codes: H01L 27/14623 Optical shielding
• CPC Class Codes: H01L 27/14643 Photodiode arrays; MOS imagers
• CPC Class Codes: H04N 25/573 the logarithmic type

Abstract

Disclosed is an image-recorder chip having a multiplicity of image cells provided with field-effect transistors disposed in the form of a two dimensional array and having a readout logic. This present invention is directed to the object of projection of high input signal dynamics onto reduced output signal dynamics, and is distinguished by the arrangement of the light-sensitive element of each image cell being connected between one electrode of a first MOS transistor and gate of a second MOS transistor, and by the other electrode of the first MOS transistor being connected to the one pole of a voltage supply source.

Claims

1. An image cell having field-effect transistors, providing a light-sensitive element in particular, for an image-recorder chip comprising a multiplicity of such image cells disposed in form of a two-dimensional array and a readout logic, for transference of high input signal dynamics onto reduced output signal dynamics, wherein the light-sensitive element of the image cell (11 . . . 23) being connected between one electrode of a first MOS transistor (M1) and the gate Of a second MOS transistor (M2), a control voltage is applied to the gate of said first MOS transistor (M1) by which a compression of said input signal dynamics is controlled, another electrode of said first MOS transistor (M1) is connected to one polarity side (V_ss) of a voltage supply source, and an output signal being tapped at a second electrode of said second MOS transistor (2) by a control voltage by means of which the compression of said input signal dynamics can be controlled being applied to the gate of said first MOS transistor (M1), by the other electrode of said first MOS transistor (M1) being connected to the one pole (V_ss) of a voltage supply source, and by the output signal being tapped at the second electrode of said second MOS transistor (2).

2. An image cell according to claim 1,

wherein one electrode of said first MOS transistor (M1) being the source electrode and the other electrode being the drain electrode.

3. An image cell according to claim 1 or 2,

wherein said light-sensitive element being the one electrode of said first MOS transistor (M1).

4. An image cell according to claim 1,

wherein a drain electrode and said gate of said first MOS transistor (M1) being short-circuited and applied to a fixed potential (V_ss) so that a logarithmic characteristic line is yielded.

5. An image cell according to claim 1,

wherein said second MOS transistor (M2) being connected as a source follower and being a part of a first readout amplifier.

6. An image cell according to claim 5,

further comprising a two-stage designed second readout amplifier (M3a, M4), being connected with said readout amplifier, wherein a first stage of said two-stage designed Second readout amplifier (M3a, M4) picks up little quiescent current during non-readout and a second stage (M4) is designed as a power stage which only becomes active for readout.

7. An image cell according to claim 5 or 6,

further comprising a MOS transistor (M2a, M3) serving as a load for said source follower.

8. An image cell according to claim 1, further comprising a metal layer (A1) covering the regions which are not light-sensitive and being utilized as a power supply line.

9. An image-recorder chip having image cells according to claim 1,

further comprising a readout logic (row_-- sel, 31 . . . 33) permitting random access to the individual image cells (11 . . . 23).

10. An image cell comprising field-effect transistors, providing a light-sensitive element in particular, for an image-recorder chip comprising a multiplicity of such image cells disposed in form of a two-dimensional array and a readout logic, for the transformation of high input-signal dynamics to reduced output-signal dynamics, wherein the light-sensitive element of each image cell (11 . . . 23) is connected between one electrode of a first MOS transistor (M1) and a gate of a second MOS transistor (M2), a control voltage is applied to a gate of said first MOS transistor in order to control compression of said input signal dynamics, the other electrode of said first MOS transistor is connected to one polarity side (V_ss, if M1 is a PMOS transistor) of a voltage supply source, and an output signal is tapped at one electrode of said second MOS transistor (M2), while its other electrode is connected to one polarity side (V_ss, if M2 is a PMOS transistor) of a voltage supply source.