Thin film semiconductor integrated circuit and method of fabricating the same

• US 5,608,251 A
• Filed: 04/02/1996
• Issued: 03/04/1997
• Est. Priority Date: 10/20/1993
• Status: Expired due to Term

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Konuma, Toshimitsu, Hiroki, Masaaki, Takemura, Yasuhiko, Yamamoto, Mutsuo, Zhang, Hongyong
• Primary Examiner(s): Monin, Jr., Donald L.
• Application Number:
  US08/626,578
• Time in Patent Office: 336 Days
• Field of Search: 257/59, 257/72, 257/410, 257/351, 257/391, 257/392, 257/393, 257/344, 257/336, 257/337, 359/54, 359/59, 359/87
• US Class Current: 257/337
• CPC Class Codes: H01L 21/02422 Non-crystalline insulating materials, e.g. glass, polymers
• CPC Class Codes: H01L 21/02532 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02686 Pulsed laser beam
• CPC Class Codes: H01L 21/28079 the final conductor layer next to the insulator being a single metal, e.g. Ta, W, Mo, Al
• CPC Class Codes: H01L 27/12 the substrate being other than a semiconductor body, e.g. an insulating body
• CPC Class Codes: H01L 27/1285 using control of the annealing or irradiation parameters, e.g. using different scanning direction or intensity for different transistors
• CPC Class Codes: H01L 29/66757 Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
• CPC Class Codes: H01L 29/78621 with LDD structure or an extension or an offset region or characterised by the doping profile
• CPC Class Codes: Y10S 438/981 Utilizing varying dielectric thickness

Abstract

In a semiconductor integrated circuit, a plurality of thin film transistors (TFTs) are formed on the same substrate having an insulating surface. Since gate electrodes formed in the TFTs are electrically insulated each other, voltages are applied independently to gate electrodes in an electrolytic solution during an anodization, to form an anodic oxide in at least both sides of each gate electrode. A thickness of the anodic oxide is changed in accordance with characteristics of the TFT. A width of high resistance regions formed in an active layer of each TFT is changed by ion doping using the anodic oxide having a desired thickness as a mask.

Claims

1. A semiconductor integrated circuit comprising:

a substrate;

an active matrix circuit which is formed on the substrate and includes at least one thin film transistor having first offset region, a first anodic oxide and impurity regions; and

driving means for driving the active matrix circuit which is formed on the substrate and includes at least another two thin film transistors each having second offset regions and a second anodic oxide,

wherein a resistance of the first offset regions is larger than that of the second offset regions, a thickness of the first anodic oxide coincides with that of the second anodic oxide and the first anodic oxide is spaced apart from the impurity regions.

2. A semiconductor integrated circuit comprising:

a substrate;

at least one thin film transistor which is formed on the substrate and provided as an active matrix circuit, the one thin film transistor having first offset regions and a first anodic oxide; and

at least another two thin film transistors which are formed on the substrate and provided as a driver circuit for driving the active matrix circuit, the another two thin film transistor each having second offset regions and a second anodic oxide,

wherein a resistance of the first offset regions is larger than that of the second offset regions, and a thickness of the first anodic oxide coincides with that of the second anodic oxide.

3. The circuit of claim 2 wherein the one thin film transistor having the first offset regions is N-channel type.

4. The circuit of claim 2 wherein the another thin film transistor having the second offset regions is P-channel type.

5. A semiconductor device comprising:

a substrate having an insulating surface;

a plurality of semiconductor regions which are formed on the insulating surface and each have at least one active layer;

an insulating film covering the semiconductor regions;

a gate electrode formed on each active layer through the insulating film; and

at least one anodic oxide formed on at least both sides of each gate electrode,

wherein a thickness of one anodic oxide formed on one gate electrode is different from that of another anodic oxide formed on another gate electrode,

wherein at least one thin film transistor having the one gate electrode is provided as an active matrix circuit and at lest another one thin film transistor having the another gate electrode is provided as a driver circuit for driving the active matrix circuit.

6. The device of claim 5 wherein one active layer formed under the one gate electrode has first offset regions, another active layer formed under the another gate electrode has second offset regions, and a width of the first offset regions is different from that of the second offset regions.

7. The device of claim 5 wherein each active layer includes a source region and a drain region.

8. The device of claim 5 wherein crystallinity of one semiconductor region is different from that of another semiconductor region.

9. The device of claim 5 wherein at least two gate electrodes are electricity insulated each other.

10. A semiconductor integrated circuit comprising:

substrate;

an active matrix circuit which is formed on the substrate and includes at least a first thin film transistor having first lightly doped drain regions, first off, set regions and a first anodic oxide; and

driving means for driving the active matrix circuit which is formed on the substrate and includes at least second and third thin film transistors, the second thin film transistor having second lightly doped drain regions, second offset regions and a second anodic oxide, the third thin film transistor having third lightly doped drain regions,

wherein a resistance of the first lightly doped drain regions is larger than that of the second and third lightly doped drain regions, a resistance of the first offset regions coincides with that of the second offset regions and a thickness of the first anodic oxide coincides with that of the second anodic oxide.

11. A thin film transistor comprising:

substrate having an insulating surface;

an active layer, formed on the insulating surface, including high concentration impurity regions and a channel forming region formed therebetween;

an insulating film formed on the active layer; and

a gate electrode formed on active layer through the insulating film,

wherein the active layer further includes low concentration regions formed between one of the high concentration impurity region and one side of the channel forming region and between another high concentration impurity region and the other side of the channel forming region, and

wherein both sides of the insulating film coincide with one side of each of the low concentration impurity regions which is in contact with each of the high concentration impurity regions.

12. A semiconductor integrated circuit comprising:

a substrate having an insulating surface; and

a plurality of thin film transistors formed on the insulating surface at least one thin film transistor being provided as an active matrix circuit, at least another one thin film transistor being provided as a driving circuit for driving the active matrix circuit,

wherein each thin film transistor comprises,

an active layer, formed on the insulating surface, including high concentration impurity regions, a channel forming region formed therebetween and low concentration regions formed between one of the high concentration impurity region and one side of the channel forming region and between another high concentration impurity region and another side of the channel forming region,

an insulating film formed on the active layer, and

a gate electrode formed on active layer through the insulating film,

wherein both sides of the insulating film coincide with one side of each of the low concentration impurity regions which is in contact with each of the high concentration impurity regions and a width of the low concentration impurity regions of one thin film transistor is different from that of the low concentration regions of another thin film transistor.

13. A semiconductor device comprising:

a substrate having an insulating surface; and

at least one thin film transistor which is formed on the insulating surface and provided as an active matrix circuit and at least another two thin film transistors which are formed on the insulating surface and provided as a driver circuit for driving the active matrix circuit, wherein the one thin film transistor has a first anodic oxide, first offset regions and impurity regions and the another two thin film transistor each have second anodic oxide and second offset regions,

wherein a width of the first offset regions is larger than that of the second offset regions,

wherein a thickness of the first anodic oxide coincides with that of the second anodic oxide, and

wherein the first anodic oxide is spaced apart from the impurity regions.

14. A semiconductor integrated circuit comprising:

a substrate;

an active matrix circuit which is formed on the substrate and includes at least one thin film transistor having first offset regions and a first anodic oxide; and

driving means for driving the active matrix circuit which is formed on the substrate and includes at least another two thin film transistors each having second offset regions and a second anodic oxide,

wherein a width of the first offset regions is larger than that of the second offset regions, and

wherein a thickness of the first anodic oxide coincides with that of the second anodic oxide.

15. A semiconductor integrated circuit comprising:

a substrate;

an active matrix circuit which is formed on the substrate and includes at least a first thin film transistor having first lightly doped drain regions, first offset regions and a first anodic oxide; and

driving means for driving the active matrix circuit which is formed on the substrate and includes at least second and third thin film transistors, the second thin film transistor having second lightly doped drain regions, second offset region and a second anodic oxide, the third thin film transistor having third lightly doped drain regions,

wherein a width of the first lightly doped drain regions is larger than that of the second and third lightly doped drain regions, a width of the first offset regions coincides with that of the second offset regions and a thickness of the first anodic oxide coincides with that of the second anodic oxide.

16. A semiconductor integrated circuit comprising:

a substrate;

at least a first thin film transistor which is formed on the substrate and provided as an active matrix circuit, the first thin film transistor having first lightly doped drain regions, first offset regions and a first anodic oxide; and

at least another second and third thin film transistors which are formed on the substrate and provided as a driver circuit for the active matrix circuit, the second thin film transistor having second lightly doped drain regions, second offset regions and a second anodic oxide, the third thin film transistor having third lightly doped drain regions,

wherein a width of the first lightly doped drain regions is larger than that of the second lightly doped drain regions, a width of the first offset regions coincides with that of the second offset regions and a thickness of the first anodic oxide coincides with that of the second anodic oxide.

17. A semiconductor integrated circuit comprising:

a substrate having an insulating surface; and

a plurality of thin film transistors formed on the insulating surface,

wherein each thin film transistor comprises,

an active layer, formed on the insulating surface, including impurity regions, a channel region formed therebetween and high resistance regions formed between one of the impurity regions and one side of the channel region and between another impurity region and the other side of the channel region,

an insulating film formed on the active layer, and

a gate electrode formed on active layer through the insulating film,

wherein a width of the high resistance regions of one thin film transistor is different from that of the high resistance regions of another thin film transistor.