Advanced transistor structures with optimum short channel controls for high density/high performance integrated circuits

• US 5,608,253 A
• Filed: 03/22/1995
• Issued: 03/04/1997
• Est. Priority Date: 03/22/1995
• Status: Expired due to Term

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Chang, Kuang-Yeh, Liu, Yowjuang W.
• Primary Examiner(s): Ngo , Ngan V.
• Application Number:
  US08/408,613
• Time in Patent Office: 713 Days
• Field of Search: 257/318, 257/364, 257/365, 257/366, 257/369, 257/372, 257/373, 257/374, 257/376, 257/401, 257/408, 257/901
• US Class Current: 257/365
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 27/0928 comprising both N- and P- wells in the substrate, e.g. twin-tub
• CPC Class Codes: H01L 29/1075 of field-effect transistors
• CPC Class Codes: H01L 29/1087 characterised by the contact structure of the substrate region, e.g. for controlling or preventing bipolar effect
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
• CPC Class Codes: H01L 29/7832 the structure comprising a MOS gate and at least one non-MOS gate, e.g. JFET or MESFET gate
• CPC Class Codes: Y10S 257/901 MOSFET substrate bias

Abstract

A novel MOS transistor structure for improving device scaling by improving short channel control includes a buried back gate beneath a channel region of the MOS transistor. A separate contact to a well that is electrically communicated to the buried back gate improves short channel controls without performance degradations. In a preferred embodiment, the back gate is grounded when turning the n-channel MOS transistor off. In alternate embodiments, the buried layer produces retrograde p wells. In some applications, multiple buried layers may be used, with one or more being planar. CMOS devices may have independent, multiple buried back gates.

Claims

1. A semiconductor device, comprising:

a substrate of a first conductivity-type;

a first active region and a second active region, each coupled to said substrate and having a second conductivity-type, said active regions separated from each other by a channel region;

a well region having said second conductivity-type separated from said active regions; and

a first buried region of said second conductivity-type, underlying said channel region and electrically coupled to said well region, for controlling a conductivity of said channel region.

2. The semiconductor device of claim 1 wherein said first conductivity-type is p-type and said second conductivity-type is n-type.

3. The semiconductor device of claim 1 wherein said first buried region underlies said active regions.

4. The semiconductor device of claim 1 wherein said well region is isolated from said active regions by an isolation region, and wherein said first buried region underlies said active regions and said isolation region.

5. The semiconductor device of claim 4 wherein said first buried region is planar.

6. The semiconductor device of claim 3 wherein said first buried region has a varying depth contour, with a first portion of said first buried region that underlies said channel region closer to said channel region than a second portion of said first buried region that underlies one of said active regions is to said one active region.

7. The semiconductor device of claim 1 further comprising:

a second buried region of said first conductivity-type disposed between said first buried region and said channel region.

8. The semiconductor device of claim 3 further comprising:

a second buried region of said first conductivity-type having a first portion disposed between said first buried region and said channel region, and having a second portion disposed between said first buried region and said active regions.

9. The semiconductor device of claim 4 further comprising:

a second buried region of said first conductivity-type having a first portion disposed between said first buried region and said channel region, having a second portion disposed between said first buried region and said active regions, and having a third portion disposed between said first buried region and said isolation region.

10. The semiconductor device of claim 9 wherein a first one of said buried regions is planar.

11. The semiconductor device of claim 10 wherein a second one of said buried region is planar.

12. The semiconductor device of claim 6 further comprising:

a second buried region of said first conductivity-type disposed between said first buried region and said channel region, and disposed between said first buried region and said active regions.

13. The semiconductor device of claim 12 wherein said second buried region has a second depth contour matching said varying depth contour of said first buried region.

14. A transistor, comprising:

a substrate of a first conductivity-type;

a first active region and a second active region, each coupled to said substrate and having a second conductivity-type, said active regions separated from each other by a channel region and providing a source and a drain of the transistor;

a gate, disposed overlying said channel region, for controlling a conductivity of carriers in said channel region;

a well region, having said second conductivity-type, separated from said active regions by an isolation region; and

a first buried region of said second conductivity-type, underlying said channel region, said active regions and said isolation region, said first buried region electrically coupled to said well region, for controlling a conductivity of said channel region responsive to a voltage reference applied to said well region.

15. The transistor of claim 14 wherein said first conductivity-type is n-type and said second conductivity-type is p-type.

16. The transistor of claim 14 wherein said first buried region has a varying depth contour, with a first portion of said first buried region that underlies said channel region closer to said channel region than a second portion of said first buried region that underlies one of said active regions is to said one active region.

17. The transistor of claim 16 further comprising:

a second buried region of said first conductivity-type having a first portion disposed between said first buried region and said channel region, having a second portion disposed between said first buried region and said active regions, and having a third portion disposed between said first buried region and said isolation region.

18. A semiconductor device, comprising:

a substrate of a first conductivity-type;

a first channel region, including;

a first active region and a second active region, each coupled to said substrate and having a second conductivity-type, said first and second active regions separated from each other by a first channel region;

a first well region having said second conductivity-type separated from said first and second active regions;

a first buried region of said second conductivity-type, underlying said channel region and electrically coupled to said well region, for controlling a conductivity of said first channel region; and

a second buried region of said first conductivity type, underlying said channel region and extending into said first well region; and

a second channel region, including;

a third active region and a fourth active region, each coupled to a second well region in said substrate and having said first conductivity-type, said third and fourth active regions in said second well separated from each other by a second channel region wherein said second well region has said second conductivity type;

a fifth active region disposed in said second well region, having said second conductivity-type, said fifth active region separated from said third and fourth active regions in said second well region;

a third buried region of said second conductivity-type, underlying said active regions in said second well region and extending across a width of said second well region, and

a fourth buried region of said first conductivity-type, underlying said active regions in said second well region and extending across a width of said second well region,

wherein said third and said fourth buried regions define a retrograde profile for said second well region.