Packaging multi-chip modules without wire-bond interconnection

• US 5,608,262 A
• Filed: 02/24/1995
• Issued: 03/04/1997
• Est. Priority Date: 02/24/1995
• Status: Expired due to Term

• Current Assignee: Bell Semiconductor, LLC (Hilco Inc. (d/b/a Hilco Global))
• Original Assignee: Lucent Technologies, Inc. (Nokia Corporation)
• Inventors: Han, Byung J., Dudderar, Thomas D., Degani, Yinon, Lyons, Alan M., Tai, King L.
• Primary Examiner(s): Mintel, William
• Assistant Examiner(s): POTTER, ROY KARL
• Application Number:
  US08/393,628
• Time in Patent Office: 739 Days
• Field of Search: 257/723, 257/778, 257/777
• US Class Current: 257/723
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48465 the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
• CPC Class Codes: H01L 2224/73207 Bump and wire connectors
• CPC Class Codes: H01L 23/13 characterised by the shape
• CPC Class Codes: H01L 23/147 Semiconductor insulating substrates semiconductor conductive substrates H01L23/4926
• CPC Class Codes: H01L 23/3107 the device being completely enclosed
• CPC Class Codes: H01L 23/4985 Flexible insulating substrates H01L23/49572 and H01L23/49855 take precedence
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01019 Potassium [K]
• CPC Class Codes: H01L 2924/01078 Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/01322 Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/10253 Silicon [Si]
• CPC Class Codes: H01L 2924/14 Integrated circuits
• CPC Class Codes: H01L 2924/15151 : the die mounting substrate comprising an aperture, e.g. for underfilling, outgassing, window type wire connections
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/15321 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/157 : with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2924/16152 : Cap comprising a cavity for hosting the device, e.g. U-shaped cap
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/19041 : being a capacitor

Abstract

Described is a novel packaging of MCM tiles without wire-bond interconnections and in a total thickness which is reduced relative to conventional MCM packaging. The MCM tile includes a substrate with a plurality of peripheral metallizations and at least one chip flip-chip mounted on the substrate. The PWB is provided with an aperture which is smaller than the size of the silicon substrate but larger than the outside dimensions of the mounted chips. The substrate is positioned on the PWB so that its ends overlap areas of the PWB adjacent the aperture and the chips fit into the aperture. Peripheral metallizations on the substrate are interconnected to metallizations on the PWB by either solder reflow technology or conductive adhesive technology.

Claims

1. A low profile multi-chip module (MCM) circuit arrangement which comprises an MCM tile and a printed wiring board (PWB), the MCM tile comprising a substrate and at least one silicon chip physically and electrically connected to the substrate,

said PWB having an aperture through the PWB and contact fingers arranged peripherally of the aperture,

the substrate of the MCM tile being larger than the aperture in the PWB, the MCM tile being positioned so that ends of the substrate overlap edges of the PWB adjacent the aperture while said at least one silicon chip is positioned within the aperture, and the substrate having peripheral metalizations which are physically and electrically interconnected to contact fingers on the PWB.

2. The MCM circuit arrangement of claim 1, in which a cavity formed by the substrate and walls of the aperture is filled with a highly conformable encapsulating material protectively enveloping interconnections between the substrate and said at least one silicon chip and between the substrate and the PWB.

3. The MCM circuit arrangement of claim 2, in which an outwardly facing surface of the substrate is protected by a "glob top".

4. The MCM circuit arrangement of claim 2 in which an outwardly facing surface of the substrate is protected by a metallized polymer film positioned about the substrate and to areas of the PWB adjacent the substrate.

5. The MCM circuit arrangement of claim 2 in which an outwardly facing surface of the substrate is protected by a cup-like cover positioned about the silicon substrate and secured to the PWB, the encapsulating material filling any space between the substrate and the cover.

6. The MCM circuit arrangement of claim 1, in which a cavity formed by the substrate and walls of the aperture is filled with a highly conformable encapsulating material protectively enveloping interconnections between the substrate and said at least one silicon chip and between the substrate and the PWB, said encapsulating material also at least partially encapsulates outer surfaces of the substrate acting as a "glob top".

7. The MCM circuit arrangement of claim 1, in which the PWB has a thin rigid form, a cup-like cover is positioned about the chip side of the MCM tile, and end flanges of the cover overlap and support the PWB at an area of the substrate-to-PWB interconnection.

8. The MCM circuit arrangement of claim 7, in which an outwardly facing surface of the substrate is enclosed by a "glob top".

9. The MCM circuit arrangement of claim 7, in which an outwardly facing surface of the substrate is enclosed by a metallized polymer film which overlaps areas of the PWB adjacent to the substrate.

10. The MCM circuit arrangement of claim 1, in which the PWB has a flexible form, a cup-like cover is positioned about the chip side of the MCM tile, portions of the PWB near the aperture are depressed into a cavity formed by the cover, and end flanges of the cover support areas of the PWB adjacent to said depressed portions.

11. The MCM circuit arrangement of claim 1, in which said PWB is a multilayer PWB, said aperture is a stepped-through aperture, the aperture through the upper level of the PWB being larger than the substrate and the aperture through the lower level of the PWB being smaller than the substrate of the MCM tile so that ends of the substrate overlap the edges of the lower level of the PWB while said at least one chip is positioned within the aperture in the lower level.

12. The MCM circuit arrangement of claim 1, in which said substrate comprises silicon.

13. The MCM circuit arrangement of claim 1, in which said at least one silicon chip is flip-chip mounted on the substrate.

14. The MCM circuit arrangement of claim 1, in which said at least one silicon chip is flip-chip mounted on the substrate by solder reflow technology.

15. The MCM circuit arrangement of claim 1, in which peripheral metallizations on the substrate are interconnected to the PWB by interconnect technology selected from the group consisting of solder reflow technology and conductive adhesive technology.