Source and sink voltage regulator for terminators

• US 5,608,312 A
• Filed: 04/17/1995
• Issued: 03/04/1997
• Est. Priority Date: 04/17/1995
• Status: Expired due to Term

• Current Assignee: Microsemi Corporation (Microchip Technology Incorporated)
• Original Assignee: Linfinity Microelectronics, Inc. (Microchip Technology Incorporated)
• Inventors: Wallace, Dean
• Primary Examiner(s): Wong, Peter S.
• Assistant Examiner(s): Patel, Rajnikant B.
• Application Number:
  US08/423,748
• Time in Patent Office: 687 Days
• Field of Search: 323/224, 323/285, 323/287, 323/316
• US Class Current: 323/224
• CPC Class Codes: G06F 13/4077 Precharging or discharging
• CPC Class Codes: H04L 25/0298 Arrangement for terminating transmission lines

Abstract

A voltage regulator for use in controllable bus terminators providing a source and a sink to a regulated output without clamping circuitry is disclosed. The regulator maintains a voltage at a node by sourcing current into the node when a cable line sinks current from the node and sinking current from the node when a cable line sources current into the node. By avoiding the use of clamping circuitry, a voltage deadband between the regulator output voltage and the clamp circuit voltage is avoided.

Claims

1. A voltage regulator, the voltage regulator comprising:

first and second operational amplifiers, each operational amplifier having an output, a noninverting input, and an inverting input, the inverting input of each operational amplifier being coupled to a reference voltage;

a first transistor having a control electrode comprising one of a base and a gate, a second electrode comprising one of an emitter and a source, and a third electrode comprising one of a collector and a drain, wherein the control electrode of the first transistor is coupled to the output of the first operational amplifier, the second electrode of the first transistor is coupled to a voltage source, and the third electrode of the first transistor is coupled to one of the noninverting input of the first operational amplifier and the noninverting input of the second operational amplifier;

a second transistor having a control electrode comprising one of a base and a gate, a second electrode comprising one of an emitter and a source, and a third electrode comprising one of a collector and a drain, wherein the control electrode of the second transistor is coupled to the output of the second operational amplifier, and the third electrode of the second transistor is coupled to one of the third electrode of the first transistor and the noninverting inputs of the first and second operational amplifier; and

a resistor coupled at a first electrode to one of the noninverting inputs of the first and second operational amplifiers, and the third electrode of the first transistor and the third electrode of the second transistor, the resistor providing an output at a second electrode, wherein

the third electrode of the first transistor is a source for current sunk from the voltage output and the third electrode of the second transistor is a sink for current sourced into the voltage output.

2. The voltage regulator of claim 1, wherein the voltage at the first electrode of the resistors is fixed to the reference voltage.

3. The voltage regulator of claim 1, wherein the first transistor is a bipolar pnp transistor and the second transistor is a bipolar npn transistor.

4. The voltage regulator of claim 1, wherein the first transistor is p-channel field effect transistor and the second transistor is an n-channel field effect transistor.

5. A method for regulating a voltage at an output, the method comprising:

providing a reference voltage at a node of inputs of first and second operational amplifiers, each operational amplifier having an output, a noninverting input, and an inverting input, the step including providing the voltage reference to the inverting inputs of the first and second operational amplifiers;

determining a voltage difference between the inverting input and noninverting input of the first operational amplifier;

determining a voltage difference between the inverting input and noninverting input of the second operational amplifier;

providing one of a first voltage and a first current to a first transistor at a control electrode, the first transistor having a control electrode comprising one of a base and a gate, a second electrode comprising one of an emitter and a source, and a third electrode comprising one of a collector and a drain, wherein the one of the first voltage and first current is based upon the voltage difference between the inverting and noninverting inputs of the first operational amplifier;

providing one of a second voltage and a second current to a second transistor at a control electrode, the second transistor having a control electrode comprising one of a base and a gate, a second electrode comprising one of an emitter and a source, and a third electrode comprising one of a collector and a drain, wherein the one of the second voltage and second current is based upon the difference between the inverting and noninverting inputs of the second operational amplifier;

generating a third current from the third electrode of the first transistor to a second node based upon one of the first voltage and the first current;

generating a fourth current from the third electrode of the second transistor to the second node based upon one of the second voltage and second current;

providing a voltage output at a first electrode of a resistor, the resistor having first and second electrodes, based upon a voltage at the second node, wherein

the third electrode of the first transistor is a source for current sunk from the voltage output and the third electrode of the second transistor is a sink for current sourced into the voltage output.

6. The method of claim 5, wherein the voltage at the second node is fixed to the reference voltage.

7. The method of claim 5, wherein the first transistor is a bipolar pnp transistor and the second transistor is a bipolar npn transistor.

8. The voltage regulator of claim 5, wherein the first transistor is p-channel field effect transistor and the second transistor is an n-channel field effect transistor.

9. A method for making a voltage regulator, the method comprising:

forming in a semiconductor die first and second operational amplifiers, each operational amplifier having an output, a noninverting input, and an inverting input, the inverting input of each operational amplifier being coupled to a reference voltage;

forming a first transistor having a control electrode comprising one of a base and a gate coupled to the output terminal of the first operational amplifier, a second electrode comprising one of an emitter and a source coupled to a voltage source, and a third electrode comprising one of a collector and a drain coupled to the noninverting input of the first operational amplifier and the noninverting input of the second operational amplifier in the same die;

forming a second transistor having a control electrode comprising one of a base and a gate coupled to the output terminal of the second operational amplifier, a second electrode comprising one of an emitter and a source, and a third electrode comprising one of a collector and a drain coupled to one of the third electrode of the first transistor and the noninverting inputs of the first and second operational amplifier in the same die; and

forming a resistor in the same die, the resistor having first and second electrodes, the first electrode being coupled to one of the noninverting inputs of the first and second operational amplifiers, and the third electrode of the first transistor and the third electrode of the second transistor, wherein

the second electrode of the resistor provides an output and the third electrode of the first transistor is a source for current sunk from the output and the third electrode of the second transistor is a sink for current sourced into the output.

10. The method of claim 9, wherein the voltage at the first electrode of the resistor is fixed to the reference voltage.

11. The method of claim 9, wherein the first transistor is a bipolar pnp transistor and the second transistor is a bipolar npn transistor.

12. The method of claim 9, wherein the first transistor is p-channel field effect transistor and the second transistor is an n-channel field effect transistor.

13. In a parallel bus terminator having a plurality of cable line connectors, each connector coupled to an enabler and a first electrode of a resistor, the resistor having first and second electrodes, wherein the improvement comprises having for each connector:

first and second operational amplifiers, each operational amplifier having an output, a noninverting input, and an inverting input, the inverting input of each operational amplifier being coupled to a reference voltage;

a first transistor having a control electrode comprising one of a base and a gate, a second electrode comprising one of an emitter and a source, and a third electrode comprising one of a collector and a drain, wherein the control electrode of the first transistor is coupled to the output of the first operational amplifier, and the third electrode of the first transistor is coupled to the noninverting input of the first operational amplifier and the noninverting input of the second operational amplifier; and

a second transistor having a control electrode comprising one of a base and a gate, a second electrode comprising one of an emitter and a source, and a third electrode comprising one of a collector and a drain, wherein the control electrode of the second transistor is coupled to the output of the second operational amplifier, and the third electrode of the second transistor is coupled to one of the third electrode of the first transistor and the noninverting inputs of the first and second operational amplifier, wherein

one of the third electrode of the first transistor and the third electrode of the second transistor provide an output to the connector through the enabler and the second electrode of the resistor, and wherein

when the connectors are enabled, the third electrode of the first transistor is a source for current sunk from the output and the third electrode of the second transistor is a sink for current sourced into the output.

14. The parallel bus terminator of claim 13, wherein the voltage at the second electrode of the resistor is fixed to the reference voltage.

15. The parallel bus terminator of claim 13, wherein the first transistor is a bipolar pnp transistor and the second transistor is a bipolar npn transistor.

16. The parallel bus terminator of claim 13, wherein the first transistor is p-channel field effect transistor and the second transistor is an n-channel field effect transistor.

17. The parallel bus terminator of claim 13, wherein each cable line connector comprises:

a node coupled to one of the enabler and the first electrode of the resistor;

a first transistor having one of an emitter and a source coupled to an output to provide a current source to negate the cable line; and

a second transistor having one of a collector and a drain coupled to the output to provide a current sink to assert the cable line.

18. An apparatus for regulating a voltage at an output, the apparatus comprising:

means for providing a reference voltage at a node of inputs of first and second operational amplifiers, each operational amplifier having an output, a noninverting input, and an inverting input, the step including providing the voltage reference to the inverting inputs of the first and second operational amplifiers;

means for determining a voltage difference between the inverting input and noninverting input of the first operational amplifier;

means for determining a voltage difference between the inverting input and noninverting input of the second operational amplifier;

means for providing one of a first voltage and a first current to a first transistor at a control electrode, the first transistor having a control electrode comprising one of a base and a gate, a second electrode comprising one of an emitter and a source, and a third electrode comprising one of a collector and a drain, wherein the one of the first voltage and first current is based upon the difference between the inverting and noninverting inputs of the first operational amplifier;

means for providing one of a second voltage and a second current to a second transistor at a control electrode, the second transistor having a control electrode comprising one of a base and a gate, a second electrode comprising one of an emitter and a source, and a third electrode comprising one of a collector and a drain, wherein the one of the second voltage and the second current is based upon the voltage difference between the inverting and noninverting inputs of the second operational amplifier;

means for generating a third current from the third electrode of the first transistor to a second node based upon one of the first voltage and the first current;

means for generating a fourth current from the third electrode of the second transistor to the second node based upon one of the second voltage and second current;

means for providing a voltage output at a first electrode of a resistor, the resistor having first and second electrodes, based upon a voltage at the second node, wherein

the third electrode of the first transistor is a source for current sunk from the voltage output and the third electrode of the second transistor is a sink for current sourced into the voltage output.

19. The apparatus of claim 18, wherein the voltage at the second node is fixed to the reference voltage.