Comparator circuit with hysteresis

• US 5,608,344 A
• Filed: 10/19/1995
• Issued: 03/04/1997
• Est. Priority Date: 10/19/1995
• Status: Expired due to Term

• Current Assignee: SGS Thomson Microelectronics Inc (STMicroelectronics NV)
• Original Assignee: SGS Thomson Microelectronics Inc (STMicroelectronics NV)
• Inventors: Marlow, C. Allen
• Primary Examiner(s): TRAN, TOAN V
• Application Number:
  US08/545,382
• Time in Patent Office: 502 Days
• Field of Search: 327/68, 327/74, 327/142, 327/143, 327/198, 327/205, 327/206, 327/534-537, 327/560, 327/63-67, 327/69-73, 327/75-89
• US Class Current: 327/206
• CPC Class Codes: H03K 2217/0018 Special modifications or use of the back gate voltage of a FET
• CPC Class Codes: H03K 3/0377 Bistables with hysteresis, e.g. Schmitt trigger non-regenerative amplitude discriminators G01R19/165
• CPC Class Codes: H03K 3/3565 Bistables with hysteresis, e.g. Schmitt trigger

Abstract

A comparator with hysteresis which has a bias current circuit, a differential input stage, and an output stage is disclosed. The differential input stage uses an analog switch to connect the body of a field effect transistors to either a first voltage or a second voltage. The analog switch in the preferred embodiment is a double-throw switch.

Claims

1. A comparator circuit comprising a bias current circuit, a differential input stage, and an output stage wherein the differential input stage comprises:

a transistor having a current path coupled to the bias current circuit, a gate for receiving an input voltage, and having a body; and

an analog switch having a control element coupled to the output stage and having a pole coupled to the body of the transistor.

2. The comparator circuit of claim 1 wherein the analog switch comprises a double-throw analog switch.

3. The comparator of claim 2 wherein the transistor is a p-channel MOSFET.

4. A comparator circuit comprising a bias current circuit, a differential input stage, and an output stage wherein the differential input stage comprises:

a first transistor having a current path coupled to the bias current circuit, a gate for receiving a first input voltage, and having a body;

an first analog switch having a control element coupled to the output stage and having a pole coupled to the body of the first transistor;

a second transistor having a current path coupled to the bias current circuit, a gate for receiving a second input voltage, and having a body; and

a second analog switch having a control element coupled to the output stage and having a pole coupled to the body of the second transistor such that, when the output of the comparator is at a high voltage, the body of the first transistor is coupled to a first reference voltage and the body of the second transistor is coupled to a second reference voltage, and, when the output of the comparator is low, the body of the first transistor is coupled to a second reference voltage and the body of the second transistor is coupled to a first reference voltage.

5. The comparator of claim 4 wherein the first analog switch is a double-throw analog switch.

6. The comparator of claim 4 wherein the first transistor comprises a p-channel MOSFET.

7. A comparator circuit comprising a bias current circuit, a differential input stage, and an output stage wherein the differential input stage comprises:

a first transistor having a current path coupled to the bias current circuit, a gate for receiving a first input voltage, and having a body; and

a means for coupling the body of the first transistor to a first reference voltage when the output stage is at a high output level and to a second reference voltage when the output stage is at a low output level.

8. The comparator of claim 7 wherein the means for coupling the body of the first transistor to a first voltage reference comprises an analog switch.

9. The comparator circuit of claim 8 wherein the analog switch comprises a double-throw analog switch.

10. The comparator circuit of claim 7 wherein the first transistor comprises an n-channel MOSFET transistor.

11. A method for generating hysteresis in a comparator comprising the steps of:

coupling the body of a transistor of a differential pair to a first voltage when an output of the comparator is at a high voltage; and

coupling the body of the transistor of the differential pair to a second voltage when the output of the comparator is at a low voltage.

12. The method of claim 11 wherein the step of coupling the body of a transistor to a first voltage is performed with an analog switch.

13. The method of claim 12 wherein the analog switch is a double-throw switch.

14. The method of claim 11 wherein the first voltage is fixed bias voltage.

15. A reset circuit which includes a comparator circuit comprising a bias current circuit, a differential input stage, and an output stage;

wherein the differential input stage comprises;

a first transistor having a current path coupled to the bias current circuit, a gate for receiving a first input voltage, and having a body; and

an first analog switch having a control element coupled to the output stage and having a pole coupled to the body of the first transistor.

16. The comparator circuit of claim 15 wherein the first analog switch comprises a double-throw analog switch.

17. The comparator of claim 16 wherein the first transistor is a p-channel MOSFET.