Method of finding a critical path in a circuit by considering the clock skew
First Claim
1. Method for producing a circuit layout having plural signal propagation paths, the method comprising the steps:
- attributing a weight to each of said paths, said weight including clock skew information; and
comparing the weight of each of said paths to identify a critical path, said step of attributing a weight further including steps of;
weighting at least one instance using a clock signal path delay and a data path delay; and
subtracting the clock signal path delay of said at least one instance from said data path delay of said at least one instance to determine said weight of said at least one instance.
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Abstract
The present invention is directed to a method of designing and fabricating a circuit layout which revolutionizes the manner by which critical weights of a circuit layout are assessed. In accordance with exemplary embodiments, a critical path is assessed on the basis of both a physical delay associated with a data propagation path and with respect to any clock skew which exists with respect to the data propagation path. A critical path can be a path having the shortest physical length from an input node to an output node if the clock skew along this path results in a high probability of a race condition. In accordance with exemplary embodiments, clock skew is assessed by determining the time differential between the arrival of a clock signal at a given data source instance and the arrival of a clock signal at a given data destination instance.
60 Citations
18 Claims
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1. Method for producing a circuit layout having plural signal propagation paths, the method comprising the steps:
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attributing a weight to each of said paths, said weight including clock skew information; and comparing the weight of each of said paths to identify a critical path, said step of attributing a weight further including steps of; weighting at least one instance using a clock signal path delay and a data path delay; and subtracting the clock signal path delay of said at least one instance from said data path delay of said at least one instance to determine said weight of said at least one instance. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15)
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16. Method for producing a circuit layout comprising the steps of:
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determining a clock delay along a clock signal path from at least one clock source of the circuit layout to at least one instance of the circuit layout; determining a data path delay along a data path from at least one data source of the circuit layout to said at least one instance; and weighting said data path of said at least one instance using said clock delay and said data path delay, said step of weighting further including the step of; subtracting the clock signal path delay of said at least one instance from said data path delay of said at least one instance to determine said data path weight. - View Dependent Claims (17, 18)
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Specification