Fast internal reference cell trimming for flash EEPROM memory

• US 5,608,679 A
• Filed: 01/31/1996
• Issued: 03/04/1997
• Est. Priority Date: 06/02/1994
• Status: Expired due to Term

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Javanifard, Johnny, Mi, James Q., Dilley, Dennis
• Primary Examiner(s): YOO, DO H
• Application Number:
  US08/594,415
• Time in Patent Office: 398 Days
• Field of Search: 365/201, 365/189.07, 365/185, 365/900, 365/185.22, 365/185.33
• US Class Current: 365/185.03
• CPC Class Codes: G06F 2201/81 Threshold
• CPC Class Codes: G11C 11/5621 using charge storage in a floating gate
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 16/04 using variable threshold transistors, e.g. FAMOS
• CPC Class Codes: G11C 16/3454 Arrangements for verifying correct programming or for detecting overprogrammed cells
• CPC Class Codes: G11C 16/3459 Circuits or methods to verify correct programming of nonvolatile memory cells
• CPC Class Codes: G11C 2029/5006 Current
• CPC Class Codes: G11C 2211/5621 Multilevel programming verification
• CPC Class Codes: G11C 2211/5634 Reference cells
• CPC Class Codes: G11C 29/50 Marginal testing, e.g. race, voltage or current testing
• CPC Class Codes: G11C 29/52 Protection of memory contents; Detection of errors in memory contents

Abstract

A method for storing a charge on memory devices which includes the steps of providing a first charging pulse to a memory device to charge the device to a first level less than a final level; testing the value of the charge to determine whether the charge is greater than the first level; if the value of the charge is less than the first level, providing a second set of charging pulses to the memory device, each of the pulses of the second set of pulses having a duration which is a fraction of the duration of the first pulse and a value sufficient to charge the device to the first level; testing the value of the charge to determine whether the charge is greater than the first level after each pulse of the second set of pulses; and once the charge has tested greater than the first level, providing a third set of charging pulses to terminals of the memory device, each of the pulses of the third set of pulses having a duration which is a fraction of the duration of the pulses of the second set of pulses and a value such that the charge furnished by each pulse is approximately equal to an allowable variation of the charge from the final value.

Claims

1. A method for storing a charge on a memory device comprising the steps of:

providing a first charging pulse to terminals of a memory device, the first charging pulse having a first charging voltage and a first duration such that the memory device stores close to a first amount of charge that is less than a target amount of charge;

testing the memory device to determine whether the memory device stores more than the first amount of charge;

if the first amount of charge is less than a first level, providing a second set of charging pulses to terminals of the memory device to charge the memory device close to the first level, each charging pulse of the second set of charging pulses having a second duration which is less than the first duration and a second charging voltage having a second amount of charge such that the memory device stores close to the first amount of charge;

testing the memory device to determine whether the memory device stores more than the first amount of charge after each charging pulse of the second set of charging pulses;

once the memory device has been determined as storing more than the first amount of charge, providing a third set of charging pulses to terminals of the memory device until the memory device stores the target amount of charge, each of the charging pulses of the third set of charging pulses having a third duration which is less than the second duration and a third charging voltage such that a third amount of charge furnished by each charging pulse of the third set of charging pulses is approximately equal to an allowable variation from the target amount of charge; and

testing the memory device to determine whether the memory device stores more than the target amount of charge after each charging pulse of the third set of charging pulses.

2. A method as claimed in claim 1 in which the memory device is a flash EEPROM field effect transistor device.

3. A method as claimed in claim 2 in which all charging pulses are applied to a gate terminal of the flash EEPROM field effect transistor device while drain and source terminals are held at constant values.

4. A method as claimed in claim 3 in which the first charging pulse has the first charging voltage sufficient to place the memory device in a saturation range of operation, each charging pulse of the second set of charging pulses having a charging voltage that is greater than a charging voltage of an immediately preceding charging pulse, and wherein the third charging voltage is equal to a charging voltage of a last charging pulse of the second set of charging pulses.

5. A method for storing a charge on a flash EEPROM field effect memory device comprising the steps of:

providing a first charging pulse to a gate terminal of the memory device while holding drain and source terminals constant, the first charging pulse having a first charging voltage and a first duration such that the memory device stores close to a first amount of charge that is less than a target amount of charge, the first amount of charge being sufficient to place the memory device in the saturation range of operation;

testing the memory device to determine whether the memory device stores more than the first amount of charge;

if the memory device stores less than the first amount of charge, providing a second set of charging pulses to the gate terminal of the memory device, each charging pulse of the second set of charging pulses having a second duration which is less than the first duration and a second charging voltage having a second amount of charge such that the memory device stores close to the first amount of charge;

testing the memory device to determine whether the memory device stores more than the first amount of charge after each charging pulse of the second set of charging pulses;

once the memory device has been determined as storing more than the first amount of charge, providing a third set of charging pulses to terminals of the memory device, each charging pulse of the third set of charging pulses having a third duration which is less that the second duration and a third charging voltage such that a third amount of charge furnished by each charging pulse of the third set of charging pulses is approximately equal to an allowable variation from the target amount of charge; and

testing the memory device to determine whether the memory device stores more than the target amount of charge after each charging pulse of the third set of charging pulses.

6. A method as claimed in claim 5 in which each charging pulse of the second set of charging pulses has a charging voltage that is greater than a charging voltage of an immediately preceding charging pulse, and wherein the third charging voltage is equal to a charging voltage of a last charging pulse of the second set of charging pulses.

7. A method as claimed in claim 5 wherein the second duration is equal to, one-forth the first duration, and wherein the third duration is one-tenth the second duration.

8. A method as claimed in claim 5 in which the charging voltage of each charging pulse of the second set of charging pulses is one-tenth volt greater than the charging voltage of the immediately preceding charging pulse.

9. A method for programming a memory cell such that a memory device stores close to a target amount of charge, comprising the steps of:

applying a first charging pulse to the memory device for a first duration such that the memory device stores a first amount of charge that is less than the target amount of charge;

applying a second set of charging pulses to the memory device such that the memory device stores a second amount of charge that is less than the target amount of charge and greater than the first amount of charge, wherein each charging pulse of the second set of charging pulses is applied for a second duration that is less than the first duration; and

applying a third set of charging pulses to the memory device such that the memory device stores a third amount of charge that is within an allowable variation of the target amount of charge, wherein each charging pulse of the third set of charging pulses is applied for a third duration that is less than the second duration.

10. The method of claim 9, further comprising the steps of:

testing the memory device after applying the first charging pulse to determine whether the first amount of charge exceeds the second amount of charge, wherein the step of applying the second set of charging pulses is not performed if the first amount of charge exceeds the second amount of charge;

testing the memory device after applying each charging pulse of the second set of charging pulses to determine whether the memory device stores the second amount of charge, wherein the charging pulses of the second set of charging pulses continue to be applied until the memory device is determined as storing the second amount of charge; and

testing the memory device after applying each charging pulse of the third set of charging pulses to determine whether the memory device stores the third amount of charge, wherein the charging pulses of the third set of charging pulses continue to be applied until the memory device is determined as storing the third amount of charge.

11. The method of claim 10, wherein a charging voltage of each charging pulse of the second set of charging pulses is greater than a charging voltage of an immediately previous charging pulse.

12. The method of claim 9, wherein the memory device is a flash EEPROM memory cell and the first charging pulse has a first charging voltage, the first charging voltage and the first duration are selected such that the flash EEPROM memory cell is placed in a saturation range.

13. The method of claim 12, wherein the second duration is approximately one-fourth the first duration, and the third duration is approximately one-tenth the second duration.

14. The method of claim 13, wherein a charging voltage of each charging pulse of the second set of charging pulses is one-tenth volt greater than a charging voltage of an immediately previous charging pulse.

15. A circuit for programming a memory cell such that a memory device stores close to a target amount of charge, comprising:

means for applying a first charging pulse to the memory device for a first duration such that the memory device stores a first amount of charge that is less than the target amount of charge;

means for applying a second set of charging pulses to the memory device such that the memory device stores a second amount of charge that is less than the target amount of charge and greater than the first amount of charge, wherein each charging pulse of the second set of charging pulses is applied for a second duration that is less than the first duration; and

means for applying a third set of charging pulses to the memory device such that the memory device stores a third amount of charge that is within an allowable variation of the target amount of charge, wherein each charging pulse of the third set of charging pulses is applied for a third duration that is less than the second duration.

16. The circuit of claim 15, further comprising:

means for testing the memory device after applying the first charging pulse to determine whether the first amount of charge exceeds the second amount of charge, wherein said means for applying the second set of charging pulses is not performed if the first amount of charge exceeds the second amount of charge;

means for testing the memory device after applying each charging pulse of the second set of charging pulses to determine whether the memory device stores the second amount of charge, wherein the charging pulses of the second set of charging pulses continue to be applied until the memory device is determined as storing the second amount of charge; and

means for testing the memory device after applying each charging pulse of the third set of charging pulses to determine whether the memory device stores the third amount of charge, wherein the charging pulses of the third set of charging pulses continue to be applied until the memory device is determined as storing the third amount of charge.

17. The circuit of claim 16, wherein a charging voltage of each charging pulse of the second set of charging pulses is greater than a charging voltage of an immediately previous charging pulse.

18. The circuit of claim 15, wherein the memory device is a flash EEPROM memory cell and the first charging pulse has a first charging voltage, the first charging voltage and the first duration are selected such that the flash EEPROM memory cell is placed in a saturation range.

19. The circuit of claim 18, wherein the second duration is approximately one-fourth the first duration, and the third duration is approximately one-tenth the second duration.

20. The circuit of claim 15, wherein a charging voltage of each charging pulse of the second set of charging pulses is one-tenth volt greater than a charging voltage of an immediately previous charging pulse.