Method and apparatus for framing data in a digital transmission line

• US 5,608,734 A
• Filed: 11/20/1995
• Issued: 03/04/1997
• Est. Priority Date: 12/22/1993
• Status: Expired due to Fees

• Current Assignee: VLSI Technology, Inc. (Koninklijke Philips N.V.)
• Original Assignee: VLSI Technology, Inc. (Koninklijke Philips N.V.)
• Inventors: Wingen, Neal T., Sandler, Lorin H.
• Primary Examiner(s): Olms, Douglas W.
• Assistant Examiner(s): Nguyen, Chau T.
• Application Number:
  US08/560,738
• Time in Patent Office: 470 Days
• Field of Search: 370/84, 370/100.1, 370/99, 370/105, 370/105.1, 370/106, 370/108, 370/105.2, 370/105.4, 370/82, 375/365, 375/366, 375/368
• US Class Current: 370/509
• CPC Class Codes: H04J 3/0608 Detectors therefor, e.g. correlators, state machines

Abstract

A method and apparatus for framing data in digital transmission lines automatically recognizes a framing format. The apparatus preferably includes a frame alignment apparatus that can recognize any one of a number of predetermined framing formats created by framing information on an input signal. The frame alignment apparatus outputs an aligning signal to an output frame counter, which counts the data and framing information on the input signal and outputs a frame synchronization signal according to the framing format. The input signal is also coupled to an output apparatus that outputs the input signal at the clock rate of a terminating apparatus. The frame alignment apparatus preferably includes a plurality of pattern recognizers able to recognize at least one of the framing formats and a storage apparatus for storing counts of successive data and framing information that match a framing pattern. The counts are preferably used to identify the framing information on the input signal and the framing format.

Claims

1. A circuit for framing data in a digital transmission line comprising:

a buffer coupled to an input signal, said input signal including data and flaming information bits, wherein said buffer is operative to output an output signal derived from said input signal in accordance with an external output clock;

a frame aligner coupled to said input signal, wherein said frame aligner is operative to determine which of said data and framing information bits are flaming information bits and to recognize a flaming format created by said framing information bits, said framing format being one of a plurality of predetermined framing format, and wherein said frame aligner is operative to output a frame aligning signal when a framing format is recognized; and

an output counter coupled to said frame aligning signal operative to count said data and framing information bits and output a frame synchronization signal in accordance with said output clock when a framing information bit is counted.

2. A circuit as recited in claim 1 wherein said frame aligner includes a plurality of pattern recognizers, each pattern recognizer being operative to recognize at least one of said predetermined framing formats on said input signal.

3. A circuit as recited in claim 1 further comprising storage means coupled to said frame aligner for storing a count of said data and said framing information bits that identifies said framing information.

4. A circuit as recited in claim 3 wherein said input signal includes an input clock portion and an input data portion.

5. A circuit as recited in claim 4 wherein said buffer includes elastic storage means having a write address input coupled to said input clock portion of said input signal, a read address input coupled to an output clock and having a data input coupled to said input data portion, said elastic storage means operative to store a portion of said data and framing information bits to provide said output signal in synchronization with said output clock.

6. A circuit as recited in claim 3 wherein said data and framing information bits are organized into frames of equal amounts of bits, and wherein said storage means maintains a count of bits matched to a pattern associated with each of said framing formats, wherein a plurality of said counts are simultaneously maintained, and wherein said frame aligner utilizes said counts to distinguish framing information bits from data information bits in said input signal.

7. A frame alignment apparatus as recited in claim 6 wherein said organization of said data and framing bits into frames of equal amounts of bits is such that each of said frames includes a predetermined number of data and framing bits such that a bit stream is provided for each bit position of said frames, and wherein one of said counts is stored for each of said bit streams of said input signal and for each of said plurality of predetermined framing formats.

8. A circuit as recited in claim 1 wherein said output counter is reset when said frame aligning signal is received.

9. A circuit as recited in claim 8 wherein said output counter resets after a predetermined number of counts.

10. A circuit as recited in claim 9 wherein said output counter outputs said frame synchronization signal when said output counter is reset.

11. A circuit as recited in claim 1 further comprising a frame follower coupled to said frame aligner operative to monitor said input signal and check for errors in said framing information bits.

12. A circuit as recited in claim 11 wherein said frame follower includes an input counter coupled to said frame aligning signal for counting said data and said framing information bits and outputting a frame reference signal.

13. A circuit as recited in claim 12 wherein said frame follower includes a frame monitor coupled to said input counter by said frame reference signal and coupled to said input signal, said frame monitor being operative to detect errors in said framing information bits.

14. A circuit as recited in claim 11 further comprising a plurality of input signals and a plurality of frame followers corresponding to said input signals, each of said frame followers coupled to said frame aligning signal.

15. A circuit as recited in claim 1 further comprising a signal extractor coupled to said output counter and said output signal for extracting signal information from said framing information bits.

16. A circuit as recited in claim 1 wherein said predetermined framing formats include Superframe, Extended Superframe, T1 Data Multiplexer, and SLC-96 formats.

17. A frame alignment apparatus as recited in claim 1 wherein an indication of said recognized flaming format is output in said outputting step.

18. A digital reception apparatus for framing data in a digital transmission line, the apparatus comprising:

a buffer coupled to an input signal, said input signal including data bits and framing information bits, wherein said data bits are organized in flames and said framing information bits designate successive flames of said data bits, and wherein said buffer is operative to output data bits derived from said input signal in accordance with an external output clock;

a frame aligner coupled to said input signal, said frame aligner being operative to determine one of a plurality of possible framing formats from said data and flaming information bits by determining which of said data and flaming information bits are flaming information bits; and

an output counter coupled to said frame aligner for counting said data and framing information bits and for outputting a frame synchronization signal, said frame synchronization signal identifying said flames of said output data bits.

19. A digital reception apparatus as recited in claim 18 further comprising:

a buffer for receiving data and flaming bits in a plurality of simultaneous input signals, each input signal including data and flaming bits; and

a corresponding plurality of output counters and buffers for counting and outputting bits for said plurality of input signals, wherein said frame aligner determines a framing format for each of said input signals.

20. A digital reception apparatus as recited in claim 18 wherein said frame aligner stores and simultaneously maintains a plurality of counts, each count associated with a bit position of said frames, wherein a count is incremented when said associated bit position in successive frames of said input signal matches a predetermined pattern associated with one of said plurality of framing formats associated with each of said counts.

21. A digital reception apparatus as recited in claim 20 wherein said frame aligner compares values of said counts to a predetermined threshold such that a first of said counts to be incremented to said threshold identifies a framing bit position in said input signal and determines said framing format of said data and framing bits.