Apparatus and method for error detection and correction in radio frequency identification device

• US 5,608,739 A
• Filed: 09/08/1995
• Issued: 03/04/1997
• Est. Priority Date: 09/30/1993
• Status: Expired due to Term

• Current Assignee: Round Rock Research LLC
• Original Assignee: Micron Technology, Inc.
• Inventors: Montalvo, Armando, Snodgrass, Charles K.
• Primary Examiner(s): Envall, Jr., Roy N.
• Assistant Examiner(s): BROWN, THOMAS
• Application Number:
  US08/525,944
• Time in Patent Office: 543 Days
• Field of Search: 371/32, 371/33, 371/37.1, 371/38.1, 371/39.1, 371/40.1, 371/37.7
• US Class Current: 714/785
• CPC Class Codes: H03M 13/151 using error location or error correction polynomials
• CPC Class Codes: H04L 1/0043 Realisations of complexity reduction techniques, e.g. use of look-up tables
• CPC Class Codes: H04L 1/0052 Realisations of complexity reduction techniques, e.g. pipelining or use of look-up tables
• CPC Class Codes: H04L 1/0057 Block codes H04L1/0061, H04L1/0064 take precedence
• CPC Class Codes: H04L 1/18 Automatic repetition systems, e.g. Van Duuren systems

Abstract

An RF identification system has a forward link that includes an encoder and decoder that utilize an (8, 13, 4) block code. The (8, 13, 4) block code has the ability to detect one bad bit in a thirteen-bit block, and can always detect two bad bits per block.

Claims

1. A radio frequency identification system comprising:

a source of an information signal having eight-bit blocks;

(8, 13,

     4) block code encoder means responsive to the information signal for providing a linear systematic block coded signal comprising a coded block having eight information bits and five code bits for each of the eight-bit blocks;

transmitter means responsive to the thirteen-bit linear systematic block coded signal for providing a transmitted signal;

receiver means responsive to the transmitted signal for providing a signal comprising received coded blocks;

(8, 13,

     4) linear systematic block code decoder means for decoding the received coded blocks to provide a decoded signal comprising one eight-bit decoded block for each of the received coded blocks, the eight-bit decoded blocks being generated each time there are less than two bit errors in a received coded block;

means within the decoder for determining if there are exactly two bit errors in any of the received coded blocks;

means within the decoder for correcting one bit error operable each time only one bit error occurs in any of the received coded blocks; and

identifier means responsive to the eight-bit decoded blocks for providing a return identification signal.

2. A radio frequency identification system as in claim 1 wherein the decoder means further comprises:

syndrome generator means responsive to the transmitted signal for providing a syndrome signal; and

error detection circuit means responsive to the means for determining for providing a signal indicative that a noncorrectable error in the transmitted signal has been detected.

3. A radio frequency identification system as in claim 1 wherein the first eight bits of the coded signal comprise the eight bits, i₁, i₂, i₃, i₄, i₅, i₆, i₇, and i₈, of the information signal, and the last five bits of the coded signal comprise a first parity bit, a second parity bit, a third parity bit, a fourth parity bit, and a fifth parity bit.

4. A communication error detection and correction system comprising:

a source of an information signal having eight-bit blocks;

(8, 13,

     4) block code encoder means responsive to the information signal for providing a systematic block coded signal comprising thirteen-bit blocks for each eight-bit block of the information signal;

communication means responsive to the linear systematic block coded signal for providing a communicated signal; and

(8, 13,

     4) linear systematic block code decoder means for decoding the communicated signal to provide a decoded signal having an eight-bit decoded block for each eight-bit block of the information signal, wherein the decoder means further comprises error detection circuit means for providing a signal indicative that a noncorrectable error in the communicated signal has been detected, wherein the error detection circuit means comprises eleven logic gates.

5. A communication error detection and correction system as in claim 4 wherein the eleven logic gates comprise two exclusive-OR gates, three inverters, five AND gates, and an OR gate.

6. A radio frequency identification circuit for receiving a transmitted thirteen-bit linear systematic block coded signal comprising:

memory for storing an identification code;

a linear systematic (8, 13,

     4) block code decoder means responsive to the thirteen-bit coded signal for providing a decoded signal comprising eight-bits for each block of the transmitted coded signal;

a syndrome generator responsive to the transmitted signal for providing a syndrome signal; and

an error detection circuit responsive to the syndrome signal for providing a signal indicative that a noncorrectable error in the transmitted signal has been detected; and

identifier means responsive to the decoded signal for providing a return identification signal when the decoded signal matches the stored identification code, the identifier means being disabled in response to the signal from the error detection circuit.