Apparatus and method for automatic discriminator compensation in a FSK receiver

• US 5,608,762 A
• Filed: 06/30/1993
• Issued: 03/04/1997
• Est. Priority Date: 06/30/1993
• Status: Expired due to Term

• Current Assignee: Spectralink Corporation (Mobile Devices Holdings LLC)
• Original Assignee: Spectralink Corporation (Mobile Devices Holdings LLC)
• Inventors: Maddy, Steven L.
• Primary Examiner(s): TSE, YOUNG TOI
• Application Number:
  US08/085,883
• Time in Patent Office: 1,343 Days
• Field of Search: 375/272, 375/285, 375/287, 375/317, 375/319, 375/334, 375/344, 375/346, 329/318-320, 329/349, 329/351, 329/353, 455/295-296, 455/309-310, 455/343
• US Class Current: 375/319
• CPC Class Codes: H04L 25/063 Setting decision thresholds using feedback techniques only

Abstract

A portion of a FSK signal is encoded with a central frequency (f₀) and the FSK signal is transmitted. A receiver captures the transmitted FSK signal, and demodulates the FSK signal to provide and analog data signal. The analog data signal is DC coupled to a first input of a comparator. The comparator generates a logic level binary output corresponding to the FSK signal. A second input of the comparator is coupled to a bias circuit. Preferably the bias circuit is provided by a digital to analog convertor (DAC). A control circuit detects the predetermined portion of the FSK signal in which the center of frequency is being transmitted. During the predetermined portion the control circuit samples the binary logic level output of the comparator, converts the binary logic level output to a digital error word, and uses the digital error word to control the DAC.

Claims

1. A system for automatically compensating for offset in a Frequency Shift keying (FSK) receiver, the receiver having an output providing a demodulated analog signal having the offset voltage superimposed thereon, the system comprising:

transmitter means for broadcasting a FSK signal, said FSK signal including a central frequency f0 during a predetermined portion;

a comparator having a first imput DC coupled to the receiver output, the comparator also having an output for providing a logic level binary signal corresponding to the demodulated analog signal, and a second input for receiving an analog bias votage;

control means including a counter/timer responsive to the comparator output for identifying the predetermined portion of the FSK signal and generating an enable output signal during the predetermined portion, the control means for generating an error signal on control output, the error signal based on the value of the comparator output during the predetermined portion of the FSK signal; and

bias means responsive to the error signal and having an output coupled to the second input of the comparator or providing the analog bias voltage, the bias means capable of increasing and decreasing the analog bias voltage in response to the error signal from the control means.

2. The system for automatically compensating for DC offset of claim 1 wherein the bias means comprises:

a digital to analog converter (DAC) responsive to the enable signal;

a register responsive to the enable signal and to the comparator output so as to increment the register value when the comparator output is a logic "HIGH" and decrement the register value when comparator output is a logic "LOW", wherein the register value is coupled to drive the DAC so that the analog bias voltage on the DAC output is determined from the register value; and

an enable input coupled to the enable output signal of the control means, wherein the DAC stores the current signal on the control output of the control means in the register only when the enable input is received.

3. The system for automatically compensating for DC offset of claim 2 wherein the DAC is an eight bit DAC.

4. A system for automatically compensating for DC offset of a demodulated analog Frequency Shift Keying (FSK) signal in a receiver, the system comprising:

a transmitter for broadcasting the FSK signal at radio frequency, the FSK signal including a central frequency (f₀) during a predetermined portion;

a receiver having an input for receiving the radio frequency FSK signal and an output for providing an intermediate frequency (IF) signal;

a discriminator having an input coupled to the output of the receiver and an output for providing a demodulated analog signal, wherein the demodulated analog signal includes a DC offset;

a comparator having a first input coupled to the discriminator output, the comparator also having an output for providing a logic level binary signal corresponding to the demodulated analog signal, and a second input for receiving an analog bias voltage;

means coupled to the comparator output and having an enable output for detecting the predetermined portion of the FSK signal, wherein the means for detecting generates an enable signal on the enable output during the predetermined portion of the FSK signal;

means coupled to the comparator output and having a control output bus for converting the logic level binary signal to a digital error word during the predetermined portion of the FSK signal, wherein the means for converting provides the digital error word on the control output bus; and

means coupled to the control output bus and the enable output and having an output coupled to the second input of the comparator for translating the digital error word into the analog bias voltage, wherein the means for translating increases and decreases the analog bias voltage in response to the digital error word and the enable signal.

5. The system for automatically compensating for DC offset of claim 4 wherein the means for translating is a digital to analog converter.

6. The system for automatically compensating for DC offset of claim 4 wherein the discriminator output is DC coupled to the first input of the comparator.

7. The system for automatically compensating for DC offset of claim 6 wherein the means for converting the logic level binary signal to the digital error word comprises:

a register coupled to the control output bus for storing the digital error word, wherein the register is responsive to the logic level binary signal for incrementing the digital error word by one least significant bit when the logic level binary signal is a logic "HIGH" during the predetermined portion of the FSK signal, and the register is responsive to the logic level binary signal for decreasing the digital error word by one least significant bit when the logic level binary signal is a logic "LOW" during the predetermined portion of the FSK signal.

8. The system for automatically compensating for DC offset of claim 7 wherein the means for converting changes the digital error word by only one least significant bit during every occurrence of 5 the predetermined portion of the FSK signal.

9. A method for automatically compensating for DC offset of a demodulated analog Frequency Shift Keying (FSK) signal in a receiver, the method comprising the steps of:

transmitting a FSK signal to the receiver, wherein the FSK signal comprises data during a first portion and includes a center frequency (f₀) during a second portion;

receiving the transmitted FSK signal;

demodulating the received FSK signal;

processing the second portion of the FSK signal by the steps of;

providing a first bias voltage;

comparing the demodulated second portion of the FSK signal to the first bias voltage and generating an error signal from the comparison, wherein the step of generating the error signal comprises generating a binary logic level error signal;

providing an old digital error word in a storage register;

updating the old digital error word by only one least significant bit based on the binary logic level error signal to provide a new digital error word; and

converting the new digital error word into an analog voltage, wherein the analog voltage is a second bias voltage that replaces the first bias voltage for subsequent comparing steps.