Neural processor comprising distributed synaptic cells

• US 5,608,844 A
• Filed: 06/07/1995
• Issued: 03/04/1997
• Est. Priority Date: 02/26/1992
• Status: Expired due to Fees

• Current Assignee: US Philips Corporation (Koninklijke Philips N.V.)
• Original Assignee: US Philips Corporation (Koninklijke Philips N.V.)
• Inventors: Gobert, Jean
• Primary Examiner(s): Davis, George B.
• Application Number:
  US08/487,617
• Time in Patent Office: 636 Days
• Field of Search: 395/27, 395/24, 395/22
• US Class Current: 706/42
• CPC Class Codes: G06N 3/063 using electronic means
• CPC Class Codes: G11C 11/419 Read-write [R-W] circuits

Abstract

The neural net has a physical topology independent of its functional topology. Cells, being functional equivalents of synapses, are concatenated to form a unidirectional data path. The cells are connected in parallel to a bus for individual or parallel control The respective synapses contributions to a neuron potential are individually calculated in each respective cell involved. Each cell in the concatenation either is rendered transparent or adds its contribution to the data received from the preceding cell and supplies this sum to the next cell. Preferably, the allocation of the synapses to the cells is programmable.

Claims

1. A neural processor (10) comprising:

a) input means for inputting digital signals;

b) a first plurality of storage means for storing synaptic coefficients, each synaptic coefficient defining a strength of a respective synapse connecting a respective pair of neurons;

c) a second plurality of storage means for storing neuron states;

d) an address bus (21);

e) an operation type bus (23);

f) at least one linked data path (22) for propagating data;

g) at least one free/busy path (24a, 24b) for propagating a free/busy signal; and

h) a plurality of means for computing neural potentials, comprising a plurality of synaptic cells, each synaptic cell being devoted to a respective one of the synapses, the synaptic cells being coupled in parallel to receive input signals from the address bus and the operation type bus, the synaptic cells being arranged in a chain, connected from one cell to another along the linked data path and the free/busy path, each respective synaptic cell comprising;

i) respective allocating means (31) for allocating, to the respective synaptic cell, a free/busy state propagated by the linked free/busy path;

ii) respective addressing means (33) for

A) storing an address identifying the respective synaptic cell, the address comprising a source neuron identifier (51) and a destination neuron identifier (53), and

B) comparing the address to a current address (SID, DID) appearing on the address bus (21) for determining whether the respective synaptic cell should be activated; and

iii) respective processing means (35) for performing operations, defined by the operation type bus (22), on data received from the linked data path (22).

2. Neural processor of claim 1 wherein the address bus carries a first filtering signal (SF) and a second filtering signal (DF) which can be independently activated for addressing, respectively, either all the synaptic cells connected to a sole destination neuron or all the synaptic cells connected to a sole source neuron, and which first and second filtering signals can be simultaneously activated for addressing all the synaptic cells.

3. Neural processor of claim 2 wherein the plurality of synaptic cells is divided up in ordered groups of synaptic cells, each group having a respective linked data path.

4. Neural processor of claim 3 wherein, for each ordered group, each synaptic cell has a queue number, the linked free/busy path going through

synaptic cells that have, in each ordered group, an identical queue number and then

synaptic cells having an identical following queue number

until all synaptic cells are reached according to either an increasing or a decreasing progression.

5. Neural processor of claim 3

further comprising at least one pipeline barrier;

and

wherein the ordered groups are divided up by pieces collected in sections, which sections are separated from one another by the pipeline barrier, pieces of sections adjoining a same pipeline barrier having an identical number of synaptic cells.

6. Neural processor of claim 1 wherein the plurality of synaptic cells is divided up in ordered groups of synaptic cells, each group having a respective linked data path.

7. Neural processor of claim 6 wherein, for each ordered group, each synaptic cell has a queue number, the linked free/busy path going through

synaptic cells that have, in each ordered group, an identical queue number and then

synaptic cells having an identical following queue number

until all synaptic cells are reached according to either an increasing or a decreasing progression.

8. Neural processor of claim 6

further comprising at least one pipeline barrier;

and

wherein the ordered groups are divided up by pieces collected in sections, which sections are separated from one another by the pipeline barrier, pieces of sections adjoining a same pipeline barrier having an identical number of synaptic cells.

9. Neural processor of claim 7

further comprising at least one pipeline barrier;

and

wherein the ordered groups are divided up by pieces collected in sections, which sections are separated from one another by the pipeline barrier, pieces of sections adjoining a same pipeline barrier having an identical number of synaptic cells.