Add-in board with enable-disable expansion ROM for PCI bus computers

• US 5,608,876 A
• Filed: 05/22/1995
• Issued: 03/04/1997
• Est. Priority Date: 05/22/1995
• Status: Expired due to Term

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Holland, William G., Cohen, Ariel, Logan, Joseph F., Parash, Avi
• Primary Examiner(s): Harvey, Jack B.
• Assistant Examiner(s): Lefkowitz, Sumati
• Application Number:
  US08/447,022
• Time in Patent Office: 652 Days
• Field of Search: 395/281, 395/284, 395/830
• US Class Current: 710/300
• CPC Class Codes: G06F 12/0684 with feedback, e.g. presence or absence of unit detected by addressing, overflow detection

Abstract

An adapter or add-in card for use in a peripheral component interconnect (PCI) computer includes a universal module which couples the card to the PCI bus. The module includes a set of selectively programmable configuration registers which are loaded by a microprocessor on the adapter. A circuit arrangement on the module issues a command which inhibits the PCI processor from accessing the configuration registers until fully loaded. Another circuit arrangement presents the Expansion ROM base address register as a `read/write` register or a read only register with all bits set to logical "0 " to the PCI computer. If the Expansion ROM base address register is presented as a read only register with all bits set to "0 ", the PCI computer concludes that no Expansion ROM exists on the add-in card, and its contents are not shadowed into the memory of the PCI computer. This disabling of the Expansion ROM causes memory space to be conserved in the computer. If the Expansion ROM is presented as a read/write register with non-zero values, the PCI computer concludes that an Expansion ROM exists and "shadows" its contents into the memory of the PCI computer.

Claims

1. An add-in board for using in a PCI computer system comprising:

a first bus;

a subassembly task generator means, coupled to the first bus, for performing predetermined functions to accomplish a desired task;

a non-volatile storage coupled to the first bus, said non-volatile storage containing an Expansion ROM for storing code to be executed by a processor not connected to the first bus;

an on-board microprocessor coupled to the first bus, said on-board microprocessor configuring the add-in board to allow the processor not connected to the first bus access or no access to the Expansion ROM;

a PCI bus interface chip for interconnecting to the first bus and a second bus, said PCI bus interface chip including at least one control register with at least one bit to be activated by the on-board microprocessor;

a PCI Expansion ROM base address register accessible by the processor not connected to the first bus; and

a logic means being responsive to the logical state of the at least one bit for allowing a predetermined bit pattern to be outputted from the PCI Expansion ROM base address register wherein the predetermined bit pattern is an indication of no Expansion ROM to the processor not connected to the first bus.

2. The add-in board of claim 1 wherein the processor not connected to the first bus is a PCI processor located in the PCI computer system.

3. The add-in board of claim 1 or 2 wherein the sub-assembly task generator means performs predetermined functions to accomplish desired tasks of a communication controller which attaches said PCI system to a LAN.

4. The add-in board of claim 3 wherein the LAN includes ethernet, token ring, FDDI or ATM.

5. The add-in board of claim 1 or 2 wherein the sub-assembly task generator means performs predetermined functions to accomplish desired tasks of a device controller.

6. The add-in board of claim 5 wherein the device controller controls display, multimedia subsystem, disk, subassembly or co-processor subsystems.

7. The add-in board of claim 1 wherein the Expansion ROM occupies from 2k bytes to 16k bytes of the non-volatile storage.

8. The add-in board of claim 1 wherein the second bus includes a PCI bus.

9. The add-in board of claim 1 wherein the logic means includes a logical OR circuit.

10. The add-in board of claim 9 further including a multiplexor circuit means (MUX) having an input coupled to PCI Expansion ROM base address register;

a means for providing the predetermined bit pattern connected to another input of the MUX; and

a PCI address/data MUX/DEMUX interconnecting the output of said multiplexor circuit means to the PCI bus.

11. The add-in board of claim 10 further including an Expansion ROM decode logic means coupled to the output of the multiplexor circuit means and the PCI address/data MUX/DEMUX, said Expansion ROM decode logic means monitoring the multiplexor circuit means and PCI address/data MUX/DEMUX and if an address in said multiplexor circuit means matches an address outputted from said PCI address/data MUX/DEMUX, executes a read or write of the PCI Expansion ROM.

12. The add-in board of claim 9 wherein the predetermined bit pattern includes all logical 0s.

13. The add-in board of claim 10 further including a conductor means interconnecting a pin on the add-in board and an input to the OR logic circuit.

14. An interface subsystem for coupling an add-in board to the PCI bus of a PCI computer comprising:

at least one control register with at least one bit to be set to a first state if an Expansion ROM on said add-in board is to be disabled;

a register means for receiving and storing a first predetermined bit pattern generated by the PCI computer, with said first predetermined bit pattern indicating the availability of the Expansion ROM;

a means for generating a second predetermined bit pattern, indicating the Expansion ROM is not available;

a selection circuit means for selecting the first predetermined bit pattern or the second predetermined bit pattern in response to the state of a control signal; and

a logical means for monitoring the state of said at least one bit, and if said at least one bit is set to a first predetermined state, setting the control signal to a first electrical state wherein the selection circuit means selects the second predetermined bit pattern and forwards said second predetermined bit pattern to the PCI computer which examines the second predetermined bit pattern, and if set to a first predetermined value, indicates the presence of no Expansion ROM on said add-in board.

15. The interface subsystem of claim 14 wherein the first predetermined state includes a logical "1".

16. The interface subsystem of claim 15 wherein the first predetermined value includes logical "0s".

17. The interface subsystem of claim 14 further including if the at least one bit is set to a second predetermined state, setting the control signal to a second electrical state wherein the selection circuit means selects the first bit pattern and forwards said first bit pattern to the PCI computer which examines the first bit pattern and if set to a second predetermined value, indicates the presence of an Expansion ROM on said add-in board.

18. The interface subsystem of claim 17 wherein the second predetermined value includes logical "1s".