Active cache for a microprocessor
First Claim
Patent Images
1. An active cache for use in a microprocessor based system comprising:
- a) memory bus means for accessing a random access memory,b) request-reception means for receiving a memory request, at least a portion of an address of said random access memory and data from a microprocessor,c) memory control means for performing read operations independent of said microprocessor on said random access memory, coupled to said memory bus means and said request-reception means,c) address decode means coupled to said request-reception means, said address decode means determining if said memory request is to enable said memory control means,d) means for enabling said memory control means if said address decode means indicates an active cache request and disabling said memory control means otherwise, ande) storage means for caching memory data of said random access memory for access by said microprocessor, wherein cacheability is enhanced.
5 Assignments
0 Petitions
Accused Products
Abstract
An active cache memory for use with microprocessors is disclosed. The cache is external to the microprocessor and forms a second level cache which is novel in that it is capable of performing transfers from external random access memory independently of the microprocessor. The cache also provides the ability to encache misaligned references and to transfer data to the microprocessor in bursts.
-
Citations
3 Claims
-
1. An active cache for use in a microprocessor based system comprising:
-
a) memory bus means for accessing a random access memory, b) request-reception means for receiving a memory request, at least a portion of an address of said random access memory and data from a microprocessor, c) memory control means for performing read operations independent of said microprocessor on said random access memory, coupled to said memory bus means and said request-reception means, c) address decode means coupled to said request-reception means, said address decode means determining if said memory request is to enable said memory control means, d) means for enabling said memory control means if said address decode means indicates an active cache request and disabling said memory control means otherwise, and e) storage means for caching memory data of said random access memory for access by said microprocessor, wherein cacheability is enhanced. - View Dependent Claims (2, 3)
-
Specification
-
- Resources
Litigation Campaign Assessment
Thank you for your request. You will receive a custom alert email when the Litigation Campaign Assessment is available.
×
-
Current AssigneeEricsson AB (Telefonaktiebolaget LM Ericsson)
-
Original AssigneeAlantec Corp. (Cornhill Corp. Holdings LLP)
-
InventorsWakerly, John F.
-
Primary Examiner(s)Robertson, David L.
-
Application NumberUS08/489,411Time in Patent Office634 DaysField of Search395/445, 395/460, 395/465, 395/403US Class Current711/118CPC Class CodesG06F 12/0879 Burst modeG06F 12/0886 Variable-length word accessG06F 12/0897 with two or more cache hier...
