Method of making back gate contact for silicon on insulator technology

• US 5,610,083 A
• Filed: 05/20/1996
• Issued: 03/11/1997
• Est. Priority Date: 05/20/1996
• Status: Expired due to Term

• Current Assignee: Chartered Semiconductor Manufacturing Pte Ltd (GlobalFoundries, Inc.)
• Original Assignee: Chartered Semiconductor Manufacturing Pte Ltd (GlobalFoundries, Inc.)
• Inventors: Sundaresan, Ravis H., Chan, Lap, Wei, Che-Chia
• Primary Examiner(s): Niebling, John
• Assistant Examiner(s): Booth, Richard A.
• Application Number:
  US08/650,697
• Time in Patent Office: 295 Days
• Field of Search: 437/21, 437/41, 437/52, 437/60, 437/918
• US Class Current: 438/155
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688

Abstract

A process for creating a back gate contact, in an SOI layer, that can easily be incorporated into a MOSFET fabrication recipe, has been developed. The back gate contact consists of a etched trench, lined with insulator, and filled with doped polysilicon. The polysilicon filled trench electrically connects the semiconductor substrate to overlying metal contacts.

Claims

1. A method for fabricating silicon devices, in a layer of silicon on a first insulator layer, on a semiconductor substrate, incorporating a back gate contact for said silicon devices, to said semiconductor substrate, comprising the steps of:

providing said semiconductor substrate;

providing said first insulator layer, on said semiconductor substrate;

providing said silicon layer, on said first insulator layer, on said semiconductor substrate;

growing a second insulator layer on a surface of said silicon, on said first insulator layer;

depositing a first polysilicon layer on said second insulator layer;

ion implanting a first conductivity imparting dopant into said first polysilicon layer;

patterning of said first polysilicon layer to form polysilicon structures;

growing a first sidewall oxide on exposed surfaces of said polysilicon structures;

depositing a third insulator layer on said polysilicon structures, and between said polysilicon structures;

first photoresist masking to expose a region of said first sidewall oxide, and underlying said polysilicon structures;

anisotropic etching of said third insulator layer, of said first sidewall oxide, of said polysilicon structures, of said second insulator layer, and of said silicon layer, in said exposed region of said first photoresist masking, to create a trench;

removal of said first photoresist masking;

growing a second sidewall oxide on exposed surfaces of said polysilicon structures, and exposed surfaces of said silicon layer, in said trench;

depositing a fourth insulator layer at the bottom and sides of said trench, and one a surface of said third insulator layer;

anisotropic etching of said fourth insulator layer to form first insulator sidewall spaces on sides of said trench, while removing said fourth insulator layer from the surface of said third insulator layer;

anisotropic etching of said first insulator layer, at a bottom of said trench, to extend said trench to a surface of said semiconductor substrate, while thinning said third insulator layer;

depositing a second polysilicon layer in said trench, and on the surface of said third insulator layer;

removal of said second polysilicon layer from the surface of said third insulator layer;

removal of said third insulator layer, and of said first sidewall oxide, from the surface of said polysilicon structures;

depositing a third layer of polysilicon on the surface of said third insulator layer, between said polysilicon structures, on the surface of said polysilicon structures, and on a surface of said second polysilicon layer, in said trench;

ion implanting a second conductivity imparting dopant into said third polysilicon layer;

patterning;

of said third polysilicon layer, overlying said second polysilicon layer, in said trench, to form said back gate contact structure;

of said third polysilicon layer, overlying said third insulator layer, to form a polysilicon resistor structure; and

of said third polysilicon layer and said first polysilicon layer, overlying said second insulator layer, to form polysilicon gates;

depositing a fifth insulator layer;

anisotropic etching of said fifth insulator layer to form second insulator sidewall spacers on sides of said polysilicon gates, on sides of said polysilicon resistor structure, and on sides of said back gate contact structure;

a second photoresist masking to expose only a region of said silicon layer, and said polysilicon gates;

ion implanting a third conductivity imparting dopant into said region of said silicon layer, not covered by said polysilicon gates, and not covered by said second photoresist masking;

removal of said second photoresist masking;

deposition of a sixth insulator layer;

opening contact holes in said sixth insulator layer, to said back gate contact structure, to said polysilicon resistor structure, and to said region of said silicon layer;

deposition of a metal; and

forming metal contact structures to said back gate contact structure, to said polysilicon resistor structure, and to said region of said silicon layer.

2. The method of claim 1, wherein said silicon layer, on insulator layer, produced by a SIMOX, (Separation of IMplanted OXygen) process, is a P type layer, with a resistivity between about 5 to 25 ohm-cm, having a <

100>

crystallographic orientation, and a thickness between about 800 to 3000 Angstroms.

3. The method of claim 1, wherein said second insulator layer is silicon dioxide, thermally grown in an oxygen --steam ambient, at a temperature between about 800°

to 900°

C., to a thickness between about 50 to 200 Angstroms.

4. The method of claim 1, wherein said first polysilicon layer is deposited using LPCVD processing, at a temperature between about 600°

to 650°

C., to a thickness between about 1500 to 4000 Angstroms.

5. The method of claim 1, wherein said first conductivity imparting dopant is phosphorous, ion implanted at an energy between about 30 to 70 Kev., at a dose between about 1E14 to 1E16 atoms/cm².

6. The method of claim 1, wherein said third insulator layer is silicon oxide, deposited using either LPCVD or PECVD processing at a temperature between about 400°

to 850°

C., to a thickness between about 3000 to 5000 Angstroms.

7. The method of claim 1, wherein said trench is reactively ion etched using CHF₃ --CF₄, to etch said third insulator layer and said first sidewall oxide layer, using Cl₂, or Cl₂ --HBr, to etch said first polysilicon layer, again using CHF₃ --CF₄, to etch said second insulator layer, and again using Cl₂, or Cl₂ --HBr, to etch said silicon layer, on said first insulator layer.

8. The method of claim 1, wherein said fourth insulator layer, used to form said first insulator sidewall spacers, on sides of said trench, is silicon oxide, deposited using LPCVD or PECVD processing, at a temperature between about 400°

to 850°

C., to a thickness between about 2000 to 5000 Angstroms.

9. The method of claim 1, wherein said first insulator layer, at bottom of said trench, is removed via reactive ion etching, using CHF₃ --CF₄.

10. The method of claim 1, wherein said second polysilicon is deposited using LPCVD processing, using in-situ doping by addition of arsine or phosphine to the silane ambient, at a temperature between about 600°

to 650°

C., to a thickness between about 1500 to 4000 Angstroms.

11. The method of claim 1, wherein said second polysilicon removal, leaving only said second polysilicon layer in said trench, is accomplished using chemical mechanical polishing.

12. The method of claim 1, wherein said third polysilicon layer is deposited using LPCVD processing, at a temperature between about 600°

to 650°

C., to a thickness between about 500 to 2000 Angstroms.

13. The method of claim 1, wherein said second conductivity imparting dopant is arsenic, or phosphorous, ion implanted at an energy between about 40 to 80 KeV, at a dose between about 1E15 to 1E16 atoms/cm².

14. The method of claim 1, wherein said third conductivity imparting dopant is arsenic, or phosphorous, ion implanted at an energy between about 40 to 80 KeV, at a dose between about 1E15 to 1E16 atoms/cm².

25. The method of claim 1, wherein said second polysilicon layer is removed from surface of said third insulator layer, via chemical mechanical polishing procedures.

15. A method for fabricating MOSFET devices, and polysilicon resistors, in a layer of silicon on a first insulator layer, on a semiconductor substrate, incorporating a back gate contact, for said MOSFET device, to said semiconductor substrate, comprising the steps of:

providing said semiconductor substrate;

providing said first insulator layer, on said semiconductor substrate;

growing a second insulator layer, on a surface of said silicon layer, to be used as a gate oxide of said MOSFET device;

depositing a first polysilicon layer on said gate oxide;

ion implanting a first conductivity imparting dopant into said first polysilicon layer;

patterning of said first polysilicon layer to form polysilicon structures;

growing a first sidewall oxide on exposed surfaces of said polysilicon structures;

depositing a third insulator layer on said polysilicon structures, and between said polysilicon structures;

first photoresist masking to expose a region of said first sidewall oxide, and underlying said polysilicon structures;

anisotropic etching of said third insulator layer, of said first sidewall oxide, of said polysilicon structures, of said gate oxide, and of said silicon layer, in an exposed region of said first photoresist masking, to create a trench;

removal of said first photoresist masking;

growing a second sidewall oxide on exposed surfaces of said polysilicon structures, and exposed surfaces of said silicon layer, in said trench;

deposition of a fourth insulator layer, on bottom and sides of said trench, and on a surface of said third insulator layer;

anisotropic etching of said fourth insulator layer to form trench sidewall spacers, on sides of said trench, and completely removing said fourth insulator layer from the surface of said third insulator layer;

anisotropic etching of said first insulator layer, at bottom of said trench, to extend said trench to a surface of said semiconductor substrate, while thinning said third insulator layer;

deposition of a second polysilicon layer in said trench, and on the surface of said third insulator layer;

removal of said second polysilicon layer from the surface of said third insulator layer, leaving a polysilicon filled trench;

removal of said third insulator layer, and said first sidewall oxide, from the surface of said polysilicon structures;

deposition of a third layer of polysilicon on the surface of said polysilicon structures, on the third insulator layer, between said polysilicon structures, and on a surface of said polysilicon filled trench;

ion implanting a second conductivity imparting dopant into said third polysilicon layer;

patterning;

of said third polysilicon layer, overlying said polysilicon filled trench, to form said back gate contact structures;

of said third polysilicon layer, overlying said third insulator layer, to form a polysilicon resistor structures; and

of said third polysilicon layer and said first polysilicon layer, overlying said gate oxide, to form polysilicon gates for said MOSFET device;

deposition of a fifth insulator layer;

anisotropic etching of said fifth insulator layer to form MOSFET sidewall spacers, on sides of said polysilicon gates, and insulator sidewall spacers on sides of, said polysilicon resistor structures, and on sides of said back gate contact structures;

a second photoresist masking to expose MOSFET regions;

ion implanting a third conductivity imparting dopant into said MOSFET regions, to create source and drain regions;

removal of said second photoresist masking;

deposition of a sixth insulator layer;

opening contact holes in said sixth insulator layer, to said back gate contact structures, to said polysilicon resistor structures, and to said regions of said MOSFET device;

deposition of a metal; and

forming metal contact structures to said back gate contact structures, to said polysilicon resistor structures, and to said regions of said MOSFET device.

16. The method of claim 15, wherein said silicon layer, on said insulator layer, is produced by a SIMOX, (Separation of IMplanted OXygen), process, and is P type with a resistivity between about 5 to 25 ohm --cm, with a <

100>

crystallographic orientation, and a thickness between about 800 to 3000 Angstroms.

17. The method of claim 15, wherein said gate oxide, of said MOSFET device, is silicon dioxide, thermally grown in an oxygen--steam ambient, at a temperature between about 800°

to 900°

C., to a thickness between about 50 to 200 Angstroms.

18. The method of claim 15, wherein said first polysilicon layer is deposited using LPCVD processing, at a temperature between about 600°

to 650°

C., to a thickness between about 1500 to 4000 Angstroms.

19. The method of claim 15, wherein said first conductivity imparting dopant is phosphorous, ion implanted at an energy between about 30 to 70 KeV, at a dose between about 1E14 to 1E16 atoms/cm².

20. The method of claim 15, wherein said third insulator layer is silicon oxide, deposited using either LPCVD or PECVD processing, at a temperature between about 400°

to 850°

C., to a thickness between about 3000 to 5000 Angstroms.

21. The method of claim 15, wherein said trench is formed via reactive ion etching, using CHF₃ --CF₄, to etch said third insulator layer and said first sidewall oxide layer, using Cl₂, or Cl₂ --HBr, to etch said polysilicon structures, using CHF₃ --CF₄, to etch said gate oxide, and Cl₂, or Cl₂ --HBr, to etch said silicon layer, on said first insulator layer.

22. The method of claim 15, wherein said fourth insulator layer, used to form said trench sidewall spacer, is silicon oxide, deposited using LPCVD or PECVD processing, at a temperature between about 400°

to 850°

C., to a thickness between about 2000 to 5000 Angstroms.

23. The method of claim 15, wherein said first insulator layer, at bottom of said trench, is removed via reactive ion etching using CHF₃ --CF₄.

24. The method of claim 15, wherein said second polysilicon layer, used to fill said trench, is deposited using LPCVD, in-situ doping, processing, adding phosphine or arsine to the silane ambient, at a temperature between about 600°

to 650°

C., to a thickness of 1500 to 4000 Angstroms.

26. The method of claim 15, wherein said third polysilicon layer is deposited using LPCVD processing, at a temperature between about 600°

to 650°

C., to a thickness between about 500 to 2000 Angstroms.

27. The method of claim 15, wherein said second conductivity dopant is arsenic, or phosphorous, ion implanted at an energy between about 40 to 80 KeV, at a dose between about 1E15 to 1E16 atoms/cm².

28. The method of claim 15, wherein said third conductivity dopant, used to form said source and drain regions of said MOSFET device, is arsenic, or phosphorous, ion implanted at an energy between about 40 to 80 KeV, at a dose between about 1E15 to 1E16 atoms/cm².