Method of making a vertical FET using epitaxial overgrowth

• US 5,610,085 A
• Filed: 06/07/1995
• Issued: 03/11/1997
• Est. Priority Date: 11/29/1993
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Kim, Tae S., Yuan, Han-Tzong, Plumton, Donald L.
• Primary Examiner(s): Thomas, Tom
• Assistant Examiner(s): GURLEY, LYNNE ANN
• Application Number:
  US08/483,028
• Time in Patent Office: 643 Days
• Field of Search: 437/29, 437/40 DM, 437/41 DM
• US Class Current: 438/187
• CPC Class Codes: H01L 27/0605 integrated circuits made of compound material, e.g. AIIIBV
• CPC Class Codes: H01L 29/045 by their particular orientation of crystalline planes
• CPC Class Codes: H01L 29/1066 Gate region of field-effect devices with PN junction gate
• CPC Class Codes: H01L 29/1075 of field-effect transistors
• CPC Class Codes: H01L 29/20 including, apart from doping materials or other impurities, only AIIIBV compounds
• CPC Class Codes: H01L 29/66454 Static induction transistors [SIT], e.g. permeable base transistors [PBT]
• CPC Class Codes: H01L 29/8083 Vertical transistors SIT H01L29/7722

Abstract

A vertical field effect transistor (1700) and fabrication method with buried gates (1704) having spaced apart gate fingers and connecting structure and overgrown with source and channel epilayer followed by a doping connection of the gate fingers and connecting structure is disclosed. The vertical field effect transistor elements (1702, 1704, 1706, 1708, 1720, 1724) are made of III-V semiconductor compound grown on a germanium substrate (1726).

Claims

1. A method for fabrication of a vertical field effect transistor, comprising the steps of:

(a) providing a substrate of a first semiconductor material and first conductivity type with a first epitaxial layer of a second semiconductor material and said first conductivity type on said substrate, said second semiconductor material being different from said first semiconductor material;

(b) forming a plurality of gate fingers of said second semiconductor material and of a second conductivity type on said first epitaxial layer; and

(c) forming a second epitaxial layer on said gate fingers and said first epitaxial layer, said second epitaxial layer of said second semiconductor material and said first conductivity type and forming channels between adjacent ones of said gate fingers and a planar source over said gate fingers and said channels.

2. The method of claim 1, wherein:

(a) said first semiconductor material is germanium; and

(b) said second semiconductor material is gallium arsenide.

3. The method of claim 1, wherein:

(a) said first epitaxial layer includes a first sublayer on said substrate and a second sublayer abutting said gate fingers, wherein said first sublayer is more heavily doped than said second sublayer.

4. The method of claim 3, wherein:

(a) said source is more heavily doped than said first sublayer.

5. The method of claim 1, wherein:

(a) said substrate has a crystal orientation of (100) ±

0.5°

.

6. The method of claim 1, wherein:

(a) said step (b) of claim 1 includes removing portions of a third epitaxial layer on said first epitaxial layer.