Input/output electrostatic discharge protection circuit for an integrated circuit
First Claim
1. An Electrostatic Discharge (ESD) protection circuit for a pad of an integrated circuit, the ESD circuit comprising:
- a Silicon Controlled Rectifier (SCR) comprising;
a first transistor having a first electrode, a control electrode, and a second electrode coupled to the pad wherein said first transistor is a bipolar PNP transistor;
a second transistor having a first electrode coupled to said control electrode of said first transistor, a control electrode coupled to said first electrode of said first transistor, and second electrode coupled for receiving a first power supply voltage wherein said second transistor is a bipolar NPN transistor;
a first resistor having a first terminal coupled to the pad and a second terminal coupled to said control electrode of said first transistor;
a second resistor having a first terminal coupled to said first electrode of said first transistor and a second terminal coupled for receiving said first power supply voltage;
a third transistor for triggering said SCR having a first electrode coupled to said control electrode of said first transistor, a control electrode coupled for receiving said first power supply voltage, and second electrode coupled to said first electrode of said first transistor wherein said third transistor is disabled by said first power supply voltage, wherein an ESD event breaks-down said third transistor for enabling said SCR, and wherein said third transistor is a Metal Oxide Semiconductor Field Effect Transistor (MOSFET);
an output stage comprising;
a p-channel enhancement MOSFET having a drain, a gate coupled for receiving a first control signal, and a source coupled for receiving a second power supply voltage;
a first resistor having a first terminal coupled to said drain of said p-channel enhancement MOSFET and a second terminal coupled to the pad;
a second resistor having a first terminal coupled to the pad and a second terminal;
a n-channel enhancement MOSFET having a drain coupled to said second terminal of said second resistor, a gate coupled for receiving a second control signal, and a source coupled for receiving said first power supply voltage;
a first zener diode having an anode coupled to said gate of said p-channel enhancement MOSFET and a cathode coupled for receiving said second power supply voltage; and
a second zener diode having an anode coupled for receiving said first power supply voltage and a cathode coupled to said gate of said n-channel enhancement MOSFET.
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Accused Products
Abstract
An Input/Output (I/O) circuit (11) for an integrated circuit including Electrostatic Discharge Protection (ESD) circuitry is disclosed. A Silicon Controlled Rectifier SCR (30) is triggered by a transistor (36) which is scaled to an output transistor (24) of the I/O circuit (11) to shunt an ESD event. The SCR (30) couples between a pad (12) and a power supply line VSS. The transistor (36) is disabled. The triggering mechanism is voltage breakdown of the transistor (36) due to an ESD event. The SCR protection mechanism is process independent since the triggering mechanism is formed similarly to the output transistor (24) and thus breaks-down similarly. Zener diodes (26-29) are coupled to gates of the I/O circuit (11) and between the power supply lines. A phosphorous doping less than 5.0 E18 per cubic centimeter is used to form the cathode of zener diodes (26-29).
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Citations
12 Claims
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1. An Electrostatic Discharge (ESD) protection circuit for a pad of an integrated circuit, the ESD circuit comprising:
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a Silicon Controlled Rectifier (SCR) comprising; a first transistor having a first electrode, a control electrode, and a second electrode coupled to the pad wherein said first transistor is a bipolar PNP transistor; a second transistor having a first electrode coupled to said control electrode of said first transistor, a control electrode coupled to said first electrode of said first transistor, and second electrode coupled for receiving a first power supply voltage wherein said second transistor is a bipolar NPN transistor; a first resistor having a first terminal coupled to the pad and a second terminal coupled to said control electrode of said first transistor; a second resistor having a first terminal coupled to said first electrode of said first transistor and a second terminal coupled for receiving said first power supply voltage; a third transistor for triggering said SCR having a first electrode coupled to said control electrode of said first transistor, a control electrode coupled for receiving said first power supply voltage, and second electrode coupled to said first electrode of said first transistor wherein said third transistor is disabled by said first power supply voltage, wherein an ESD event breaks-down said third transistor for enabling said SCR, and wherein said third transistor is a Metal Oxide Semiconductor Field Effect Transistor (MOSFET); an output stage comprising; a p-channel enhancement MOSFET having a drain, a gate coupled for receiving a first control signal, and a source coupled for receiving a second power supply voltage; a first resistor having a first terminal coupled to said drain of said p-channel enhancement MOSFET and a second terminal coupled to the pad; a second resistor having a first terminal coupled to the pad and a second terminal; a n-channel enhancement MOSFET having a drain coupled to said second terminal of said second resistor, a gate coupled for receiving a second control signal, and a source coupled for receiving said first power supply voltage; a first zener diode having an anode coupled to said gate of said p-channel enhancement MOSFET and a cathode coupled for receiving said second power supply voltage; and a second zener diode having an anode coupled for receiving said first power supply voltage and a cathode coupled to said gate of said n-channel enhancement MOSFET. - View Dependent Claims (2, 3, 4, 5)
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6. An Input/Output (I/O) circuit of an integrated circuit having Electrostatic Discharge (ESD) protection circuitry for preventing an ESD event from damaging circuitry of the integrated circuit, the I/O circuit comprising:
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a first output transistor of a first conductivity type having a first electrode, a control electrode coupled for receiving a first output control signal, and a second electrode coupled for receiving a first power supply voltage; a first resistor having a first terminal coupled to a pad and a second terminal coupled to said first electrode of said first output transistor; a bipolar PNP transistor having a collector, a base, and an emitter coupled to said pad; a second resistor having a first terminal coupled to said pad and a second terminal coupled to said base of said bipolar PNP transistor; a third resistor having a first terminal coupled to said collector of said bipolar PNP transistor and a second terminal coupled for receiving said first power supply voltage; a bipolar NPN transistor having a collector coupled to said base of said bipolar PNP transistor, a base coupled to said collector of said bipolar PNP transistor, and an emitter coupled for receiving said first power supply voltage; a first transistor of said first conductivity type having a first electrode coupled to said base of said bipolar PNP transistor, a control electrode coupled for receiving said first power supply voltage, and a second electrode coupled to said collector of said bipolar PNP transistor; a second output transistor of a second conductivity type having a first electrode, a control electrode coupled for receiving a second output control signal, and a second electrode coupled for receiving a second power supply voltage; a fourth resistor having a first terminal coupled to said first electrode of said second output transistor and a second terminal coupled to said pad; a first zener diode having an anode coupled to said control electrode of said second output transistor and a cathode coupled for receiving said second power supply voltage; and a second zener diode having an anode coupled for receiving said first power supply voltage and a cathode coupled to said control electrode of said first output transistor. - View Dependent Claims (7, 8, 9, 10, 11, 12)
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Specification