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Input/output electrostatic discharge protection circuit for an integrated circuit

  • US 5,610,425 A
  • Filed: 02/06/1995
  • Issued: 03/11/1997
  • Est. Priority Date: 02/06/1995
  • Status: Expired due to Fees
First Claim
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1. An Electrostatic Discharge (ESD) protection circuit for a pad of an integrated circuit, the ESD circuit comprising:

  • a Silicon Controlled Rectifier (SCR) comprising;

    a first transistor having a first electrode, a control electrode, and a second electrode coupled to the pad wherein said first transistor is a bipolar PNP transistor;

    a second transistor having a first electrode coupled to said control electrode of said first transistor, a control electrode coupled to said first electrode of said first transistor, and second electrode coupled for receiving a first power supply voltage wherein said second transistor is a bipolar NPN transistor;

    a first resistor having a first terminal coupled to the pad and a second terminal coupled to said control electrode of said first transistor;

    a second resistor having a first terminal coupled to said first electrode of said first transistor and a second terminal coupled for receiving said first power supply voltage;

    a third transistor for triggering said SCR having a first electrode coupled to said control electrode of said first transistor, a control electrode coupled for receiving said first power supply voltage, and second electrode coupled to said first electrode of said first transistor wherein said third transistor is disabled by said first power supply voltage, wherein an ESD event breaks-down said third transistor for enabling said SCR, and wherein said third transistor is a Metal Oxide Semiconductor Field Effect Transistor (MOSFET);

    an output stage comprising;

    a p-channel enhancement MOSFET having a drain, a gate coupled for receiving a first control signal, and a source coupled for receiving a second power supply voltage;

    a first resistor having a first terminal coupled to said drain of said p-channel enhancement MOSFET and a second terminal coupled to the pad;

    a second resistor having a first terminal coupled to the pad and a second terminal;

    a n-channel enhancement MOSFET having a drain coupled to said second terminal of said second resistor, a gate coupled for receiving a second control signal, and a source coupled for receiving said first power supply voltage;

    a first zener diode having an anode coupled to said gate of said p-channel enhancement MOSFET and a cathode coupled for receiving said second power supply voltage; and

    a second zener diode having an anode coupled for receiving said first power supply voltage and a cathode coupled to said gate of said n-channel enhancement MOSFET.

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