Switched substrate bias for logic circuits

• US 5,610,533 A
• Filed: 11/29/1994
• Issued: 03/11/1997
• Est. Priority Date: 11/29/1993
• Status: Expired due to Term

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Inventors: Arimoto, Kazutami, Tsukude, Masaki
• Primary Examiner(s): Westin, Edward P.
• Assistant Examiner(s): ROSEEN, RICHARD R
• Application Number:
  US08/350,064
• Time in Patent Office: 833 Days
• Field of Search: 327/534, 327/537, 327/546, 326/33, 326/34, 257/630, 257/347
• US Class Current: 326/33
• CPC Class Codes: H01L 27/0218 of field effect structures
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H03K 19/0016 by using a control or a clock signal, e.g. in order to apply power supply
• CPC Class Codes: H03K 2217/0018 Special modifications or use of the back gate voltage of a FET

Abstract

A semiconductor circuit or a MOS-DRAM wherein converting means is provided that converts substrate potential or body bias potential between two values for MOS-FETs in a logic circuit, memory cells, and operating circuit of the MOS-DRAM, thereby raising the threshold voltage of the MOS-FETs when in the standby state and lowering it when in active state. The converting means includes a level shift circuit and a switch circuit. The substrate potential or body bias potential is controlled only of the MOS-FETs which are nonconducting in the standby state; this configuration achieves a reduction in power consumption associated with the potential switching. Furthermore, in a structure where MOS-FETs of the same conductivity type are formed adjacent to each other, MOS-FETs of SOI structure are preferable for better results.

Claims

1. A semiconductor circuit, comprising:

a MOS-FET to which a first potential or a second potential is to be supplied as substrate potential;

a voltage supplying means for supplying said first and second potentials;

a converting means for converting said substrate potential to said first potential or said second potential,

clock signal generating means for generating a control clock signal to activate said MOS-FET, wherein

said converting means includes

a level shift circuit receiving the control clock signal to control outputting a signal for conversion to said first potential or said second potential, and

a switch circuit receiving the signal output from the level shift circuit to control switching between said first potential and said second potential to supply either the first potential or second potential as said substrate potential to said MOS-FET.

2. A semiconductor circuit, comprising:

a logic circuit formed of MOS-FETs to which a first potential or a second potential is to be supplied as substrate potential;

a voltage supplying means for supplying said first and second potentials;

a converting means for converting said substrate potential to said first potential or said second potential; and

clock signal generating means for generating a control clock signal to activate said MOS-FET, wherein

said logic circuit is an inverter array in which inverter circuits consist of one conductivity type MOS-FET and the opposite conductivity type MOS-FET connected in series, and

said converting means includes

a level shift circuit receiving the control clock signal to control outputting a signal for conversion to said first potential or said second potential, and

a switch circuit receiving the signal output from the level shift circuit to control switching between said first potential and said second potential to supply either the first potential or second potential as said substrate potential to said MOS-FET, the MOS-FETs, being off in standby mode, are connected to said switch circuit.

3. The semiconductor circuit according to claim 2, wherein

said converting means supplies said first potential or said second potential as said body bias potential to said MOS-FET according to the operation state of said MOS-FET.

4. A semiconductor circuit, comprising:

a MOS-FET of SOI structure to which a first potential or a second potential is to be supplied as a body bias potential;

a voltage supplying means for supplying said first and second potentials; and

a converting means for converting said body bias potential to said first potential or said second potential.

5. The semiconductor circuit according to once of claim 4, wherein

MOS-FETs of SOI structure form a logic circuit.

6. The semiconductor circuit according to claim 4, wherein

element-isolation is performed between said MOS-FETs of SOI structure by an isolating oxide film.

7. The semiconductor circuit according to claim 4, wherein

element-isolation is performed between said MOS-FETs of SOI structure by an FS isolation layer formed by channeling off a portion of a channel layer, said FS isolation layer being connected to said converting means.

8. The semiconductor circuit according to claim 4, wherein

element-isolation is performed between said MOS-FETs of SOI structure by an isolating oxide film or an FS isolation layer formed by channeling off a portion of a channel layer, said FS isolation layer being connected to said converting means.

9. The semiconductor circuit according to claim 4, wherein

said MOS-FETs of SOI structure are MOS-FETs of the same conductivity type, wherein

element-isolation is performed between said MOS-FETs of the same conductivity type by an FS isolation layer formed by channeling off a portion of a channel layer, the FS isolation layer on each side of one of said MOS-FETs of the same conductivity type is connected to said converting means, the FS isolation layer on each side of the other of said MOS-FETs of the same conductivity type is connected to a prescribed potential, and an isolation layer formed between each FS isolation layer is supplied with another prescribed potential.

10. The semiconductor circuit according to claim 5, wherein

said logic circuit is an inverter array which consists of inverters connected in series, each of said inverters consists of a MOS-FET of one conductivity type and a MOS-FET of the other conductivity type.

11. The semiconductor circuit according to claim 10, wherein

the MOS-FETs which are nonconducting in the standby state are connected to said converting means.

12. The semiconductor circuit according to claim 11, wherein

the threshold voltage of the MOS-FETs which are conducting in the standby state is smaller than the threshold voltage of the MOS-FETs which are nonconducting in the standby state.

13. The semiconductor circuit according to claim 10, further comprising:

a main power supply line connected to a power supply;

a secondary power supply line connected to said main power supply line via a switching element;

a main ground line connected to ground; and

a secondary ground line connected to said main ground line via a switching element, wherein

said inverter array is disposed between said secondary power supply line and said secondary ground line.

14. The semiconductor circuit according to claim 13, wherein

said switching elements are MOS-FETs whose magnitude of the threshold voltage is larger than that of any of the MOS-FETs forming said logic circuit, and which are conducting in an active state.

15. The semiconductor circuit according to claim 14, wherein

the threshold voltage of the MOS-FETs which are conducting in a standby state is smaller than the threshold voltage of the MOS-FETs that are nonconducting in the standby state.