Controlled tracking of oscillators in a circuit with multiple frequency sensitive elements
First Claim
1. An oscillator circuit comprising:
- a master phase-locked loop (PLL) circuit responsive to a first reference frequency signal, the master PLL circuit comprising;
a first oscillator having an input responsive to an oscillator control signal for generating as output a first clock signal;
a first divider having an input coupled to an output of the first oscillator for dividing a frequency of the first clock signal by a first divide constant and generating as output a first frequency divided signal;
a first phase detector receiving as input the first reference frequency signal and the first frequency divided signal and generating a first phase detector output signal;
a first loop filter coupled to an output of the first phase detector for filtering the first phase detector output signal and for generating as output the oscillator control signal that is coupled to an input of the first oscillator;
a slave PLL circuit responsive to a second reference frequency signal, the slave PLL circuit comprising;
a second oscillator that is substantially identical to the first oscillator and having an input responsive to a tracking control signal for generating as output a second clock signal;
a second divider having an input coupled to an output of the second oscillator for dividing a frequency of the second clock signal by a second divide constant and generating as output a second frequency divided signal;
a second phase detector receiving as input the second reference frequency signal and the second frequency divided signal and generating a second phase detector output signal;
a second loop filter coupled to an output of the second phase detector for filtering the second phase detector output signal and for generating as output a second filtered signal that is coupled to an input of the second oscillator; and
a tracking control circuit coupled to the master PLL circuit and the slave PLL circuit to receive as input the oscillator control signal, and a tracking information signal, to generate the tracking control signal based thereon.
1 Assignment
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Accused Products
Abstract
An oscillator circuit (143) comprises a master phase-locked loop (PLL) circuit (202) that receives as input a first reference frequency signal (136) and generates a first clock signal (210) in response to an oscillator control signal (212). The oscillator circuit (143) includes a frequency sensitive slave circuit (206) having at least one frequency sensitive element (322) that is responsive to a tracking control signal (214) to generate a second clock signal (216). A tracking control circuit (204) is responsive to the oscillator control signal (212) for generating the tracking control signal (214). The tracking control signal (214) serves as a bias signal, and is connected to the frequency sensitive slave circuit (206) for achieving a fast power up sequence of the oscillator circuit (143).
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Citations
9 Claims
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1. An oscillator circuit comprising:
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a master phase-locked loop (PLL) circuit responsive to a first reference frequency signal, the master PLL circuit comprising; a first oscillator having an input responsive to an oscillator control signal for generating as output a first clock signal; a first divider having an input coupled to an output of the first oscillator for dividing a frequency of the first clock signal by a first divide constant and generating as output a first frequency divided signal; a first phase detector receiving as input the first reference frequency signal and the first frequency divided signal and generating a first phase detector output signal; a first loop filter coupled to an output of the first phase detector for filtering the first phase detector output signal and for generating as output the oscillator control signal that is coupled to an input of the first oscillator; a slave PLL circuit responsive to a second reference frequency signal, the slave PLL circuit comprising; a second oscillator that is substantially identical to the first oscillator and having an input responsive to a tracking control signal for generating as output a second clock signal; a second divider having an input coupled to an output of the second oscillator for dividing a frequency of the second clock signal by a second divide constant and generating as output a second frequency divided signal; a second phase detector receiving as input the second reference frequency signal and the second frequency divided signal and generating a second phase detector output signal; a second loop filter coupled to an output of the second phase detector for filtering the second phase detector output signal and for generating as output a second filtered signal that is coupled to an input of the second oscillator; and a tracking control circuit coupled to the master PLL circuit and the slave PLL circuit to receive as input the oscillator control signal, and a tracking information signal, to generate the tracking control signal based thereon. - View Dependent Claims (2, 3)
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4. A processor system, comprising an oscillator circuit comprising:
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a master phase-locked loop (PLL) circuit responsive to a first reference frequency signal, the master PLL circuit comprising; a first oscillator having an input responsive to an oscillator control signal for generating as output a first clock signal; a first divider having an input coupled to an output of the first oscillator for dividing a frequency of the first clock signal by a first divide constant and generating as output a first frequency divided signal; a first phase detector receiving as input the first reference frequency signal and the first frequency divided signal and generating a first phase detector output signal; a first loop filter coupled to an output of the first phase detector for filtering the first phase detector output signal and for generating as output the oscillator control signal that is coupled to an input of the first oscillator; a slave PLL circuit responsive to a second reference frequency signal, the slave PLL circuit comprising; a second oscillator that is substantially identical to the first oscillator and having an input responsive to a tracking control signal for generating as output a second clock signal; a second divider having an input coupled to an output of the second oscillator for dividing a frequency of the second clock signal by a second divide constant and generating as output a second frequency divided signal; a second phase detector receiving as input the second reference frequency signal and the second frequency divided signal and generating a second phase detector output signal; a second loop filter coupled to an output of the second phase detector for filtering the second phase detector output signal and for generating as output a second filtered signal that is coupled to an input of the second oscillator; and a tracking control circuit coupled to the master PLL circuit and the slave PLL circuit to receive as input the oscillator control signal, and a tracking information signal to generate the tracking control signal based thereon. - View Dependent Claims (5, 6)
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7. A selective call receiver, comprising a processor system having an oscillator circuit comprising:
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a master phase-locked loop (PLL) circuit responsive to a first reference frequency signal, the master PLL circuit comprising; a first oscillator having an input responsive to an oscillator control signal for generating as output a first clock signal; a first divider having an input coupled to an output of the first oscillator for dividing a frequency of the first clock signal by a first divide constant and generating as output a first frequency divided signal; a first phase detector receiving as input the first reference frequency signal and the first frequency divided signal and generating a first phase detector output signal; a first loop filter coupled to an output of the first phase detector for filtering the first phase detector output signal and for generating as output the oscillator control signal that is coupled to an input of the first oscillator; a slave PLL circuit responsive to a second reference frequency signal, the slave PLL circuit comprising; a second oscillator that is substantially identical to the first oscillator and having an input responsive to a tracking control signal for generating as output a second clock signal; a second divider having an input coupled to an output of the second oscillator for dividing a frequency of the second clock signal by a second divide constant and generating as output a second frequency divided signal; a second phase detector receiving as input the second reference frequency signal and the second frequency divided signal and generating a second phase detector output signal; a second loop filter coupled to an output of the second phase detector for filtering the second phase detector output signal and for generating as output a second filtered signal that is coupled to an input of the second oscillator; and a tracking control circuit coupled to the master PLL circuit and the slave PLL circuit to receive as input the oscillator control signal, and a tracking information signal to generate the tracking control signal based thereon. - View Dependent Claims (8, 9)
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Specification