Burst EDO memory device with maximized write cycle timing

• US 5,610,864 A
• Filed: 02/10/1995
• Issued: 03/11/1997
• Est. Priority Date: 12/23/1994
• Status: Expired due to Term

• Current Assignee: Round Rock Research LLC
• Original Assignee: Micron Technology, Inc.
• Inventors: Manning, Troy A.
• Primary Examiner(s): Nelms, David C.
• Assistant Examiner(s): LE, VU ANH
• Application Number:
  US08/386,894
• Time in Patent Office: 760 Days
• Field of Search: 365/233, 365/193, 365/189.05, 365/189.01, 365/230.01
• US Class Current: 365/193
• CPC Class Codes: G06F 12/0638 Combination of memories, e.g. ROM and RAM such as to permit replacement or supplementing of words in one module by words in another module address formation of the next microinstruction G06F9/26; masking faults in memories by using spares or by reconfiguring G11C29/70
• CPC Class Codes: G06F 2212/2022 Flash memory
• CPC Class Codes: G11C 11/407 for memory cells of the field-effect type
• CPC Class Codes: G11C 7/1018 Serial bit line access mode, e.g. using bit line address shift registers, bit line address counters, bit line burst counters
• CPC Class Codes: G11C 7/1021 Page serial bit line access mode, i.e. using an enabled row address stroke pulse with its associated word line address and a sequence of enabled column address stroke pulses each with its associated bit line address
• CPC Class Codes: G11C 7/1024 Extended data output [EDO] mode, i.e. keeping output buffer enabled during an extended period of time
• CPC Class Codes: G11C 7/1039 using pipelining techniques, i.e. using latches between functional memory parts, e.g. row/column decoders, I/O buffers, sense amplifiers
• CPC Class Codes: G11C 7/1045 Read-write mode select circuits
• CPC Class Codes: G11C 7/1078 Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
• CPC Class Codes: G11C 7/109 Control signal input circuits
• CPC Class Codes: G11C 7/1096 Write circuits, e.g. I/O line write drivers
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management

Abstract

An integrated circuit memory device is designed for high speed data access and for compatibility with existing memory systems. An address strobe signal is used to latch a first address. During a burst access cycle the address is incremented internal to the device with additional address strobe transitions. A new memory address is only required at the beginning of each burst access. Read/Write commands are issued once per burst access eliminating the need to toggle the Read/Write control line at the device cycle frequency. A transition of the Read/Write control line during a burst access is used to terminate the burst access, reset the burst length counter and initialize the device for another burst access. Write cycle times are maximized to allow for increases in burst mode operating frequencies.

Claims

1. A memory device adapted to perform a write operation to store data in the memory device, the memory device comprising:

a write operation control circuit adapted to switch control of a write operation between a write command signal and an access cycle signal during a write operation, wherein the write command signal initiates the write operation, and the access cycle signal terminates the write operation.

2. The memory device of claim 1, further comprising an array of memory elements, wherein the access cycle signal is operative to latch an address corresponding to a column of the array and to initiate an access cycle.

3. The memory device of claim 1, wherein said write operation control circuit comprises a multiplexer, said multiplexer producing a multiplexer output to control the write operation.

4. The memory device of claim 3, wherein said write operation control circuit further comprises a latch adapted to drive a latched select signal to said multiplexer to select control of the write operation.

5. The memory device of claim 1, further comprising a write command latch responsive to the access cycle signal and an externally generated write cycle control signal to create the write command signal.

6. The memory device of claim 5, further comprising a circuit to clear said write command latch at the beginning of an access cycle.

7. The memory device of claim 6, wherein said circuit to clear comprises a pulse generator.

8. A memory access cycle control circuit for a memory suitable to perform a write operation to store data in the memory device, the access cycle control circuit comprising:

circuitry to terminate a first write operation in response to initiation of an access cycle by a transition of an access cycle signal;

circuitry to initiate a second write operation in response to the transition of the access cycle signal after termination of the first write operation; and

a latch to maintain the second write operation until a subsequent transition of the access cycle signal.

9. A write cycle control circuit for a memory device, comprising:

a write cycle command latch to store a latched write cycle command in response to an access cycle signal, the access cycle signal initiating a memory access cycle; and

a pulse generator to clear said write cycle command latch in response to the access cycle signal prior to said write cycle command latch storing the write cycle command.

10. The write cycle control circuit of claim 9, further comprising:

a multiplexer, adapted to produce a write cycle control output signal, to select between the latched write cycle command and the access cycle signal to determine a state of the write cycle control output signal.

11. The write cycle control circuit of claim 9, further comprising:

an access cycle pulse generator to generate an access cycle pulse signal in response to each edge of the access cycle signal, the access cycle pulse signal having a first and a second state within each access cycle which define a first and a second portion of each access cycle.

12. The write cycle control circuit of claim 11, further comprising:

a multiplexer, adapted to produce a write cycle control output signal, to select between the latched write cycle command and the access cycle pulse signal to determine a state of the write cycle control output signal.

13. A method of writing data in a memory device, comprising the following sequence of steps:

intiating a write access cycle of the memory device with an access cycle signal;

clearing a write command latch within the memory device; and

latching a write command signal in the write command latch to control the write access cycle.

14. The method of claim 13, furhter comprising steps of:

storing data in response to said step of latching the write command signal;

initiating a further access cycle of the memory device; and

terminating said step of storing data in response to said step of initiating the further access cycle.

15. The method of claim 14, wherein said step of storing data occurs throughout a period of time nearly equal to a duration of the write access cycle.

16. The method of claim 14, further comprising a step of:

clearing the write command latch subsequent to said step of terminating.

17. The method of claim 13, further comprising steps of:

storing data in response to said step of latching the write command signal;

initiating a read cycle of the memory device; and

terminating said step of storing data in response to said step of initiating the read cycle.

18. The method of claim 17, further comprising:

clearing the write command latch subsequent to said step of terminating.

19. The method of claim 13, further comprising:

storing data in response to said step of latching the write command signal;

terminating a burst access of the memory device; and

terminating said step of storing data in response to said step of terminating the burst access.

20. The method of claim 19, further comprising:

clearing the write command latch subsequent to said step of terminating said step of storing.