Method and device for channel selection

• US 5,610,911 A
• Filed: 09/28/1994
• Issued: 03/11/1997
• Est. Priority Date: 09/28/1993
• Status: Expired due to Fees

• Current Assignee: NEC Corporation
• Original Assignee: NEC Corporation
• Inventors: Suzaki, Tetsuyuki, Ishikawa, Hajime
• Primary Examiner(s): Kizou, Hassan
• Application Number:
  US08/314,047
• Time in Patent Office: 895 Days
• Field of Search: 370/55, 370/100.1, 370/105, 370/105.1, 370/105.2, 370/105.4, 370/106, 370/112, 370/85.15, 375/106, 375/114, 375/116, 375/362, 375/365, 375/366, 375/368, 375/371, 359/135, 340/825.03, 340/825.2
• US Class Current: 370/503
• CPC Class Codes: H04J 14/08 Time-division multiplex systems
• CPC Class Codes: H04J 3/0602 Systems characterised by the synchronising information used

Abstract

The present invention provides a method and device for channel selection for setting at least one channel among N channels as a reference channel, detecting temporal location of the reference channel in a reception side, selecting an arbitrary channel using a relative time difference between the detected temporal location of the reference channel and that of the channel to be selected.

Claims

1. A method for channel selection among a plurality of channels, wherein at least one of said plurality of channels is a reference channel and at least one of said plurality of channels is a data channel, said reference channel including discrimination information which distinguishes said reference channel from said data channel, said method comprising the steps of:

(a) generating a transmission signal by time division multiplexing bit by bit said plurality of channels and transmitting said transmission signal;

(b) detecting from said transmitted transmission signal, a temporal location of said reference channel based on said discrimination information; and

selecting an arbitrary channel based on a relative time difference between said temporal location of said reference channel and a temporal location of said arbitrary channel;

generating a synchronization signal according to a transmission speed of said data channel, wherein said synchronization signal includes a phase with respect to said reference channel;

changing said phase of said synchronization signal to a reference phase synchronized with said reference channel; and

shifting said reference phase a number of time slots corresponding to said relative time difference to change said reference phase of said synchronization signal to a phase synchronized with said arbitrary channel.

2. A method for channel selection among a plurality of channels, wherein at least one of said plurality of channels is a reference channel and at least one of said plurality of channels is a data channel, said reference channel including discrimination information which distinguishes said reference channel from said data channel, said method comprising the steps of:

(a) generating a transmission signal by time division multiplexing bit by bit said plurality of channels and transmitting said transmission signal;

(b) detecting from said transmitted transmission signal, a temporal location of said reference channel based on said discrimination information; and

selecting an arbitrary channel based on a relative time difference between said temporal location of said reference channel and a temporal location of said arbitrary channel;

wherein said plurality of channels each corresponds to one of a plurality of data transmission speeds, and said step (b) further comprises;

generating a plurality of synchronization signals each in accordance with said corresponding one of said plurality of data transmission speeds, wherein each of said synchronization signals includes a phase with respect to said reference channel;

decoding said discrimination information from said transmission signal by changing the phase of at least one of said synchronization signals and thereby detecting said reference channel;

adjusting the phase of said synchronization signals to said reference channel and setting these synchronization signals as reference synchronization signals; and

selecting an arbitrary channel, when having received a request of selecting an arbitrary channel, by selecting a reference synchronization signal according to said arbitrary channel data transmission speed among said reference synchronization signals, counting number of time slots from said reference channel to said arbitrary channel, shifting the phase of said selected reference synchronization signal said number of the time slots and synchronizing said selected reference synchronization signal with said arbitrary channel.

3. A data receiver for receiving a transmission signal generated by time division multiplexing N channels, wherein at least one of said channels is a reference channel and wherein said reference channel includes discrimination information to distinguish said reference channel from non-reference channels, said data receiver comprising:

a means for extracting a transmission clock signal from said transmission signal;

a means for identifying said reference channel from said transmission signal based on said discrimination information;

a means for generating a synchronization signal in accordance with a data transmission speed of said transmission signal, said synchronization signal having a phase with respect to the reference channel, and wherein said means for identifying said reference channel is controlled by the phase of said synchronization signal, and wherein the phase of said synchronization signal is stored as a reference phase when said means for identifying said reference channel has detected said reference channel, and wherein upon a request for a selection of an arbitrary channel, the phase of said synchronization signal is synchronized with said arbitrary channel by counting a number of time slots from said reference channel to said arbitrary channel, and shifting said reference phase said number of the time slots; and

a means for extracting data on said arbitrary channel from said transmission signal based on said synchronization signal.

4. The data receiver of claim 3, wherein said means for generating a synchronization signal comprises:

a frequency divider for generating said synchronization signal by dividing said transmission clock signal into 1/N;

a phase changing circuit for changing the phase of said synchronization signal based on a control signal and synchronizing the phase of said synchronization signal with an arbitrary channel; and

a phase control circuit for directing said means for identifying said reference channel to detect said reference channel by outputting said control signal to change the phase of said synchronization signal, and wherein the phase of said synchronization signal is stored as a reference phase when said means for identifying said reference channel has detected said reference channel, and wherein upon a request for a selection of an arbitrary channel, the phase of said synchronization signal is synchronized with said arbitrary channel by counting a number of time slots from said reference channel to said arbitrary channel and outputting said control signal to shift said reference phase said number of the time slots.

5. The data receiver of claim 3, wherein said means for generating a synchronization signal comprises:

a frequency divider for generating said synchronization signal by frequency dividing said transmission clock signal into 1/N; and

a phase control circuit for changing the phase of said synchronization signal by resetting said frequency divider, and directing said means for identifying said reference channel to detect said reference channel, and wherein the phase of said synchronization signal is stored as a reference phase when said means for identifying said reference channel has detected said reference channel, and wherein upon a request for a selection of an arbitrary channel, a number of time slots from said reference channel to said arbitrary channel is counted and said frequency divider is reset so as to delay said reference phase said number of time slots.

6. The data receiver of claim 3, wherein said means for generating a synchronization signal comprises:

a variable frequency divider and a phase control circuit;

said variable frequency divider having frequency division modes, 1/N and 1/(N+1), for generating said synchronization signal by frequency dividing said transmission clock signal in a frequency division mode, wherein said frequency division mode is 1/(N+1) if an instruction is received from said phase control circuit to change the mode to 1/(N+1) for a specified number of cycles and otherwise said frequency division mode is 1/N; and

said phase control circuit changing the phase of said synchronization signal by outputting an instruction to said variable frequency divider to change the frequency mode to 1/(N+1) for a specified number of cycles, and directing said means for identifying said reference channel to detect said reference channel, and wherein the phase of said synchronization signal is stored as a reference phase when said means for identifying said reference channel has detected said reference channel, and wherein upon a request for a selection of an arbitrary channel, a number of time slots from said reference channel to said arbitrary channel is counted and, outputting said number of time slots as said number of cycles to said variable frequency divider.

7. The data receiver of claim 3, for receiving a transmission signal having a plurality of reference channels, wherein:

a corresponding plurality of said means for identifying said reference channels are provided, and wherein each of said means for identifying detects a respective reference channel; and

said means for generating a synchronization signal stores the phase of the synchronization signal when the first reference channel is detected by said plurality of said means for identifying said reference channels as said reference phase.

8. The data receiver of claim 3, wherein said plurality of channels each corresponds to one of a plurality of data transmission speeds and wherein at least one of said data transmission speeds differs from at least one other of said data transmission speeds, comprising:

a second means for generating a second synchronization signal according to an arbitrary data transmission speed based on said transmission clock signal, wherein the phase of said second synchronization signal is synchronized to the phase of said reference channel that has been detected by said means for identifying said reference channel, and wherein upon a request of selection of a channel according to said second synchronization signal, a number of time slots from said reference channel to the channel requested to be selected is counted, and wherein the phase of said second synchronization signal synchronized to said reference channel is shifted said number of the time slots to synchronize said second synchronization signal with said channel requested to be selected; and

a second means for extracting data of said channel requested to be selected from said transmission signal based on said second synchronization signal that is phase synchronized with said requested channel.

9. A data receiver for receiving a transmission signal that has a data transmission speed and is generated by time division multiplexing a plurality of channels, wherein said plurality of channels includes at least one reference channel and wherein said reference channel includes discrimination information and wherein at least said reference channel has a transmission speed different than the transmission speed of the other of said plurality of channels, said data receiver comprising:

a means for extracting a transmission clock signal from said transmission signal;

a means for detecting said reference channel from said transmission signal based on said discrimination information;

a means for generating a first synchronization signal in accordance with a data transmission speed of said reference channel and for generating a second synchronization signal according to a data transmission speed of other channels, wherein said means for detecting said reference channel detects said reference channel by controlling the phase of said first synchronization signal, and wherein the phase of said second synchronization signal is adjusted to the detected reference channel, and wherein upon a request of selection of an arbitrary channel, said second synchronization signal is selected according to a data transmission speed of said arbitrary channel, and wherein a number of time slots from said reference channel to said arbitrary channel is counted, and the phase of said second synchronization signal adjusted to said reference channel is shifted said number of the time slots to synchronize said second synchronization signal with said arbitrary channel; and

a means for extracting data of said arbitrary channel from said transmission signal based on said second synchronization signal.

10. The data receiver of claim 9, wherein said means for generating said first and second synchronization signals comprises:

a plurality of frequency dividers, said frequency dividers generating respectively, by frequency dividing said data transmission speed of said transmission signal, said first and second synchronization signals;

a plurality of phase changing circuits, each of said phase changing circuits for adjusting the phase of said synchronization signals, the phase of said second synchronization signal being adjusted to said arbitrary channel by changing the phase of said second synchronization signal based on a control signal; and

a plurality of phase control circuits, each of said phase control circuits for changing the phase of said synchronization signals by outputting said control signal, wherein the phase of said second synchronization signal is adjusted to the phase of said reference channel, and wherein upon a request for selection of said arbitrary channel, a number of time slots from said reference channel to said arbitrary channel is counted and said control signal is output to shift the phase of said second synchronization signal said number of the time slots.

11. A data transmitter and receiver comprising:

(a) a data transmission means including;

(1) a discrimination information generation means for generating discrimination information to discriminate a reference channel;

(2) a time division multiplexing means for generating transmission data by time division multiplexing said discrimination information and data of other channels, the total number of channels being equal to N;

(b) a data reception means including;

(1) a transmission clock signal extraction means for extracting a transmission clock signal from said transmission signal;

(2) a reference channel detection means for detecting said reference channel from said transmission signal based on said discrimination information;

(3) a synchronization signal phase control means for generating a synchronization signal according to a data transmission speed based on said transmission clock signal, wherein said reference channel detection means is controlled by the phase of said synchronization signal, and wherein the phase of the synchronization signal is stored as a reference phase when said reference channel detection means has detected said reference channel, and wherein upon a request for a selection of an arbitrary channel, a number of time slots from said reference channel to said arbitrary channel is counted, and said reference phase is shifted said number of the time slots to synchronize the phase of said synchronization signal with said arbitrary channel; and

(4) a data extraction means for extracting data of said arbitrary channel based on said synchronization signal that is phase synchronized with said arbitrary channel.

12. The data transmitter and receiver of claim 11, wherein said synchronization signal phase control means comprises:

a frequency divider for generating said synchronization signal by frequency dividing said transmission clock signal into 1/N;

a phase changing circuit for synchronizing the phase of said synchronization signal to an arbitrary channel by changing the phase of said synchronization signal based on a control signal;

a phase control circuit for directing said reference channel detection means to detect said reference channel by outputting said control signal to change the phase of said synchronization signal, and wherein the phase of said synchronization signal is stored as a reference phase when said reference channel detection means has detected said reference channel, and wherein upon a request for a selection of an arbitrary channel, a number of time slots from said reference channel to said arbitrary channel is counted, and said control signal is output to shift said reference phase said number of the time slots.

13. The data transmitter and receiver of claim 11, wherein said synchronization signal phase control means comprises:

a frequency divider for generating said synchronization signal by frequency dividing said transmission clock signal into 1/N;

a phase control circuit for changing the phase of said synchronization signal by resetting said frequency divider, and directing said reference channel detection means to detect said reference channel, and wherein the phase of said synchronization signal is stored as a reference phase when said reference channel detection means has detected said reference channel, and wherein upon a request for a selection of an arbitrary channel, a number of time slots from said reference channel to said arbitrary channel is counted and said frequency divider is reset so as to delay said reference phase said number of time slots.

14. The data transmitter and receiver of claim 11, wherein said synchronization signal phase control means comprises:

a variable frequency divider and a phase control circuit;

said variable frequency divider having frequency division modes, 1/N and 1/(N+1), for generating synchronization signal by frequency dividing said transmission clock signal in a frequency division mode, wherein said frequency division mode is 1/(N+1) if an instruction is received from said phase control circuit to change the mode to 1/(N+1) for a specified number of cycles and otherwise said frequency division mode is 1/N; and

said phase control circuit changing the phase of said synchronization signal by outputting an instruction to said variable frequency divider to change the frequency mode to 1/(N+1) for a specified number of cycles, and directing said reference channel detection means to detect said reference channel, and wherein the phase of said synchronization signal is stored as a reference phase when said reference channel detection means has detected said reference channel, and wherein upon a request for a selection of an arbitrary channel, a number of time slots from said reference channel to said arbitrary channel is counted and, outputting said number of time slots as said number of cycles to said variable frequency divider.

15. The data transmitter and receiver of claim 11, for receiving a transmission signal having a plurality of reference channels, wherein:

a corresponding plurality of reference channel detection means are provided, wherein each of said reference channel detection means detects respective reference channel; and

said synchronization signal phase control means stores the phase of the synchronization signal when the first reference channel is detected by said plurality of reference channel detection means as said reference phase.

16. A data receiver for receiving a transmission signal that has a data transmission speed and is generated by time division multiplexing a plurality of channels, wherein said plurality of channels includes at least one reference channel, and wherein said reference channel includes discrimination information and wherein at least said reference channel has a transmission speed different than the transmission speed of the other of said plurality of channels, said data receiver comprising:

a transmission clock signal extraction means for extracting a transmission clock signal from said transmission signal;

a reference channel detection means for detecting said reference channel from said transmission signal based on said discrimination information;

a synchronization signal phase control means for generating a plurality of synchronization signals in accordance with data transmission speeds of said channels which are based on said transmission clock signal, wherein said reference channel detection means detects said reference channel by controlling the combination of the phases of said synchronization signals, and wherein the phases of said synchronization signals are adjusted to the phase of the detected reference channel, and wherein upon a request for a selection of an arbitrary channel, a number of time slots from said reference channel to said arbitrary channel is counted, and the phases of said synchronization signals adjusted to said reference channel are adjusted said number of the time slots to synchronize said combination of phases of said synchronization signals with said arbitrary channel; and

a data extraction means for extracting data of said arbitrary channel from said transmission signal based on said synchronization signals that are phase synchronized with said arbitrary channel.

17. The data receiver of claim 16, wherein said synchronization signal phase control means comprises:

a plurality of frequency dividers, said frequency dividers generating respectively, by frequency dividing the data transmission speed of said transmission signal, said synchronization signals;

a plurality of phase changing circuits, each of said phase changing circuits for adjusting the phase of a respective synchronization signal to said arbitrary channel by changing the phase of said respective synchronization signal based on a control signal; and

a phase control circuit for changing the phases of said synchronization signals by outputting said control signals, wherein the phases of said synchronization signals is adjusted to the phase of said reference channel, and wherein upon a request of selection of said arbitrary channel, a number of time slots from said reference channel to said arbitrary channel is counted and said control signals is output to shift the phases of said synchronization signals said number of the time slots.