×

Shared buffer memory switch for an ATM switching system and its broadcasting control method

  • US 5,610,914 A
  • Filed: 05/24/1995
  • Issued: 03/11/1997
  • Est. Priority Date: 05/24/1994
  • Status: Expired due to Fees
First Claim
Patent Images

1. A shared buffer memory switch used for an ATM (Asynchronous Transfer Mode) switching system including a cell multiplexer for multiplexing and outputting incoming cells from a plurality of input ports onto a time division multiplex data bus, a shared buffer memory for storing the cells on said time division multiplex data bus, and a cell demultiplexer for demultiplexing and distributing the cells having been output onto said time division multiplex data bus from said shared buffer memory to a plurality of output ports, said shared buffer memory switch comprising:

  • a first address pointer queue of a first-in-first-out memory for storing addresses of idle area in said shared buffer memory;

    a plurality of second address pointer queues of a first-in-first-out memory, one of said plurality of second address pointer queues being provided for each of said output ports for storing an address of a storage area in said shared buffer memory in which contents of the cell to be output to the corresponding output port are stored;

    a broadcast registration table which stores broadcasting destination information corresponding to a routing information of each of broadcasting cells; and

    a shared buffer memory control for reading a broadcasting destination information from said broadcast registration table corresponding to the routing information of the broadcasting cell when a cell being processed is a broadcasting cell,for reading an address of said shared buffer memory from said first address pointer queue, for writing said address into all said second address pointer queues corresponding to output ports which are indicated by said broadcasting destination information, for writing contents of said broadcasting cell with said broadcasting destination information into an area of said shared buffer memory indicated by said address in a writing cycle,for reading an address from one of said second address pointer queues corresponding to a routing information being processed, and for reading contents of said broadcasting cell with said broadcasting destination information from said shared buffer memory in said address, for copying and outputting said broadcasting cell to said time division multiplex data bus in a reading cycle,for resetting information of destination, corresponding to an output port currently being processed, from said broadcasting destination information, and for writing said broadcasting cell again into the same address in said shared buffer memory with said broadcasting destination information when at least one destination is contained in said broadcasting destination information.

View all claims
  • 1 Assignment
Timeline View
Assignment View
    ×
    ×