Optimal L2 tracking in a SPS receiver under encryption without knowledge of encryption timing characteristics

• US 5,610,984 A
• Filed: 11/22/1995
• Issued: 03/11/1997
• Est. Priority Date: 11/22/1995
• Status: Expired due to Term

• Current Assignee: Trimble Navigation Limited (Trimble Inc.)
• Original Assignee: Trimble Navigation Limited (Trimble Inc.)
• Inventors: Lennen, Gary R.
• Primary Examiner(s): Cain, David C.
• Application Number:
  US08/526,885
• Time in Patent Office: 475 Days
• Field of Search: 380/9, 380/34, 380/49, 375/200, 375/201, 375/205, 375/207, 375/208, 342/352, 342/357
• US Class Current: 380/270
• CPC Class Codes: G01S 19/32 Multimode operation in a single same satellite system, e.g. GPS L1/L2
• CPC Class Codes: G01S 19/40 Correcting position, velocity or attitude

Abstract

The optimal design of the SPS Receiver is disclosed. The optimal SPS Receiver includes the digital filter with adjustable characteristics in each digital processing channel. The optimal design of the SPS Receiver is achieved by adjusting the filter characteristics of each digital filter to match the observed spectrum of the unknown W code satellite signals. The matching operation can be performed for each satellite channel with its own secret W code signal.

Claims

1. A system for optimal correlation processing of L1 and L2 signals received from a SPS satellite by a SPS RECEIVER, said system comprising:

a RECEIVING MEANS for receiving a known C/A code modulated on L1 carrier frequency, for receiving an unknown Y code modulated on L1 carrier frequency signal, and for receiving an unknown Y code modulated on L2 carrier frequency signal from at least one satellite;

wherein said received L1, and L2 signals contain propagation noise; and

wherein said Y code comprises a known P code and an unknown W code; and

at least one DIGITAL CHANNEL PROCESSING MEANS for;

(1) locally generating replica of said C/A code modulated on L1 carrier frequency signal;

(2) locally generating replica of said P code modulated on L1 carrier frequency signal, wherein said locally generated replica of L1 signal does not contain propagation noise;

(3) locally generating replica of said P code modulated on L2 carrier frequency signal, wherein said locally generated replica of L2 signal does not contain propagation noise;

(4) extracting of an estimate of said Y code from said L1 signal, and from said L2 signal, wherein said estimate signals contain propagation noise;

(5) correlating a locally generated replica of C/A code with the received L1 code for obtaining an estimate of L1 group delay (L1 pseudo-range) and L1 carrier phase;

(6) removing said P code from said locally extracted estimate of said L1 Y code to obtain a locally extracted estimate of said L1 W code;

(7) removing said P code from said locally extracted estimate of said L2 Y code to obtain a locally extracted estimate of said L2 W code;

(8) filtering estimate of said L1 W code by a DIGITAL FILTER 1 with filter characteristics substantially similar to the W code frequency spectrum with no requirement for the filter characteristics to have any knowledge of the secret W code timing characteristics;

(9) filtering estimate of said L2 W code by a DIGITAL FILTER 2 with filter characteristics substantially similar to the W code frequency spectrum with no requirement for the filter characteristics to have any knowledge of the secret W code timing characteristics; and

10) multiplying said filtered estimates of said L1 W-code with said filtered early, late, and punctual estimates of L2 W-code and integrating the result over a time period greater than a millisecond to ensure that the resulting correlated signal has a sufficient power for closing the L2-code and L2-carrier tracking loops.

2. The system of claim 1, wherein said RECEIVING MEANS further comprises:

a dual frequency patch ANTENNA MEANS for receiving said L1 and L2 satellite signals;

a FILTER/LNA MEANS conductively connected to said ANTENNA MEANS for performing filtering and low noise amplification of said L1 and L2 signals, wherein said FILTER/LNA determines the signal/noise ratio of the received signals L1 and L2;

a DOWNCONVERTER MEANS conductively connected to said FILTER/LNA MEANS for mixing and converting said L1 and L2 signals; and

an IF PROCESSOR MEANS conductively connected to said DOWNCONVERTER MEANS for transforming said converted L1 and L2 signals into digitally sampled quadrature versions of L1 and L2 signals (IL1, QL1, IL2, QL2).

3. The system of claim 2 further comprising a MASTER OSCILLATOR MEANS and a FREQUENCY SYNTHESIZER MEANS conductively connected to said MASTER OSCILLATOR MEANS, conductively connected to said IF PROCESSOR MEANS, conductively connected to said DOWNCONVERTER MEANS, and conductively connected to at least one said DIGITAL CHANNEL PROCESSING MEANS, wherein said FREQUENCY SYNTHESIZER MEANS generates several timing signals.

4. The system of claim 3, wherein said FILTER/LNA MEANS further comprises:

a POWER SPLITTER MEANS connected to said ANTENNA MEANS for power splitting a single L1/L2 signal received by said ANTENNA MEANS into two separate L1 and L2 signals;

two separate BANDPASS FILTER MEANS connected to said POWER SPLITTER MEANS for filtering said L1 and L2 signals independently; and

a POWER COMBINER MEANS connected to said separate BANDPASS FILTER MEANS for power combining said L1 and L2 signals into one combined signal L1/L2 before feeding said combined L1/L2 signal into said LNA;

wherein said LNA outputs amplified and filtered combined L1/L2 signal.

5. The system of claim 3, wherein said FREQUENCY SYNTHESIZER MEANS further comprises:

a PHASE DETECTOR MEANS for comparing phases of two signals, first said signal being an output signal from said MASTER OSCILLATOR MEANS, second said signal being generated by said FREQUENCY SYNTHESIZER MEANS local reference signal, wherein minimum voltage output signal from said PHASE DETECTOR MEANS represents maximum phase alignment of said two signals;

a LOOP FILTER MEANS connected to said PHASE DETECTOR MEANS for filtering out high frequency voltage noise, wherein an output LOOP FILTER MEANS voltage signal includes a low frequency voltage noise;

a VOLTAGE CONTROLLED OSCILLATOR (VCO) MEANS connected to said LOOP FILTER MEANS, wherein a voltage signal at the input of said VCO causes frequency change in said VCO output signal, and wherein said VCO nominal output signal is locked to said reference signal; and

wherein said VCO nominal output signal is used as 1st local oscillator (LO1) signal;

a first DIVIDER MEANS connected to said VCO to divide said VCO output signal to obtain 2nd local oscillator (LO2) signal;

a second DIVIDER MEANS connected to said first DIVIDER MEANS to divide said 2nd LO2 signal to obtain sampling clock (SCLK); and

a third DIVIDER MEANS connected to said second DIVIDER MEANS to divide said 2nd LO2 signal to obtain a signal MSEC, wherein said signal MSEC is used for measurement of local reference time.

6. The system of claim 3, wherein said FREQUENCY SYNTHESIZER MEANS further comprises:

a "Divide by 5" block;

a PHASE DETECTOR MEANS connected to said block "Divide by 5" for comparing 5 MHz input signal from said MASTER OSCILLATOR MEANS with 5 MHZ signal from said "Divide by 5" block, wherein minimum voltage output signal from said PHASE DETECTOR MEANS represents maximum phase alignment of two said 5 MHZ signals;

a LOOP FILTER MEANS connected to said PHASE DETECTOR MEANS for filtering out high frequency voltage noise;

a VOLTAGE CONTROLLED OSCILLATOR (VCO) MEANS connected to said LOOP FILTER MEANS, wherein voltage signal at the input of said VCO causes frequency change in said VCO output signal, and wherein said VCO nominal output 1400 MHz signal is locked to said 5 MHZ reference signal; and

wherein said 1400 MHz VCO output signal is used as a 1st local oscillator (LO1);

a "Divide by 8" block connected to said VCO to divide said 1400 MHZ VCO output signal by 8 to obtain a 175 MHZ signal used as a 2nd LO2;

a "Divide by 7" block connected to said "Divide by 8" block to divide said 175 MHZ signal by 7 to obtain a 25 MHZ signal used as a sampling clock (SCLK); and

a "Divide by 25000" block connected to said "Divide by 7" block to divide said 25 MHZ signal by 25000 to obtain a 1 KHZ signal (MSEC), wherein said MSEC signal is used for measurement of local reference time.

7. The system of claim 2, wherein said DOWNCONVERTER MEANS further comprises:

a POWER SPLITTER MEANS connected to said FILTER/LNA MEANS and to said FREQUENCY SYNTHESIZER MEANS for power splitting said FILTER/LNA MEANS output L1/L2 signal into two signals;

a first MULTIPLIER MEANS connected to said POWER SPLITTER MEANS for multiplying said L1 signal with said 1st LO1 signal, wherein a first mixed signal is produced;

a second MULTIPLIER MEANS connected to said POWER SPLITTER MEANS for multiplying said L2 signal with said 1st LO1 signal, wherein a second mixed signal is produced;

a first BANDPASS FILTER MEANS connected to said first MULTIPLIER MEANS for filtering said first mixed signal;

a second BANDPASS FILTER MEANS connected to said second MULTIPLIER MEANS for filtering said second mixed signal;

a first AMPLIFIER MEANS connected to said first BANDPASS FILTER MEANS for amplifying said first filtered signal; and

a second AMPLIFIER MEANS connected to said second BANDPASS FILTER MEANS for amplifying said second filtered signal.

8. The system of claim 3, wherein said IF PROCESSOR MEANS further comprises:

a first POWER SPLITTER MEANS connected to said DOWNCONVERTER MEANS and to said FREQUENCY SYNTHESIZER MEANS for power splitting said L1 signal into two signals;

a second POWER SPLITTER MEANS connected to said DOWNCONVERTER MEANS and to said FREQUENCY SYNTHESIZER MEANS for power splitting said L2 signal into two signals;

a first MULTIPLIER MEANS for multiplying said L1 signal with an inphase (I) version of said 2nd LO2 signal to produce an IL1 signal;

a second MULTIPLIER MEANS for multiplying said L1 signal with a quadrature (Q) version of said 2nd LO2 signal to produce a QL1 signal;

a third MULTIPLIER MEANS for multiplying said L2 signal with an inphase (I) version of said 2nd LO2 signal to produce an IL2 signal;

a fourth MULTIPLIER MEANS for multiplying said L2 signal with a quadrature (Q) version of said 2nd LO2 signal to produce a QL2 signal;

a first LOWPASS FILTER MEANS connected to said first MULTIPLIER MEANS for filtering said first mixed signal;

a second LOWPASS FILTER MEANS connected to said second MULTIPLIER MEANS for filtering said second mixed signal;

a third LOWPASS FILTER MEANS connected to said third MULTIPLIER MEANS for filtering said third mixed signal;

a fourth LOWPASS FILTER MEANS connected to said fourth MULTIPLIER MEANS for filtering said fourth mixed signal;

a first AMPLIFIER MEANS connected to said first LOWPASS FILTER MEANS for amplifying said IL1 signal;

a second AMPLIFIER MEANS connected to said second LOWPASS FILTER MEANS for amplifying said QL1 signal;

a third AMPLIFIER MEANS connected to said third LOWPASS FILTER MEANS for amplifying said IL2 signal;

a fourth AMPLIFIER MEANS connected to said fourth LOWPASS FILTER MEANS for amplifying said QL2 signal;

a first one-bit analog-to-digital (A/D) CONVERTER MEANS connected to said first AMPLIFIER MEANS for performing 1-bit quantization operation on said IL1 signal;

a second one-bit analog-to-digital (A/D) CONVERTER MEANS connected to said second AMPLIFIER MEANS for performing 1-bit quantization operation on said QL1 signal;

a third one-bit analog-to-digital (A/D) CONVERTER MEANS connected to said third AMPLIFIER MEANS for performing 1-bit quantization operation on said IL2 signal;

a fourth one-bit analog-to-digital (A/D) CONVERTER MEANS connected to said fourth AMPLIFIER MEANS for performing 1-bit quantization operation on said QL2 signal;

a first FLIP-FLOP MEANS (FF1) connected to said first one-bit A/D CONVERTER for sampling said IL1 signal, wherein said sampling operation is performed by clocking said IL1 signal through said FF1 at sampling clock (SCLK) rate;

a second FLIP-FLOP MEANS (FF2) connected to said second one-bit A/D CONVERTER for sampling said QL1 signal, wherein said sampling operation is performed by clocking said QL1 signal through said FF2 at sampling clock (SCLK) rate;

a third FLIP-FLOP MEANS (FF3) connected to said third one-bit A/D CONVERTER for sampling said IL2 signal, wherein said sampling operation is performed by clocking said IL2 signal through said FF3 at sampling clock (SCLK) rate; and

a fourth FLIP-FLOP MEANS (FF4) connected to said fourth one-bit A/D CONVERTER for sampling said QL2 signal, wherein said sampling operation is performed by clocking said QL2 signal through said FF4 at sampling clock (SCLK) rate.

9. The system of claim 1, wherein each said DIGITAL CHANNEL PROCESSING MEANS further comprises:

an L1 TRACKER MEANS for tracking L1 C/A code when encryption is ON and for tracking L1 P code when encryption is OFF;

an L2 TRACKER MEANS connected to said L1 TRACKER MEANS for tracking an optimal encrypted L2 tracking when encryption is ON and for tracking L2 P code when encryption is OFF; and

a MICROPROCESSOR MEANS system connected to said L1 TRACKER MEANS and to said L2 TRACKER MEANS;

wherein said L1 TRACKER MEANS is fed by digitized inphase IL1 and quadrature QL1 of L1 signal outputted by said IF PROCESSOR MEANS; and

wherein said L2 TRACKER MEANS is fed by digitized inphase IL2 and quadrature QL2 of L2 signal outputted by said IF PROCESSOR MEANS; and

wherein each said L1 and L2 TRACKER MEANS are synchronously clocked by said SCLK signal and synchronously referenced by said MSEC signal to local reference time;

said SCLK and MSEC signals being outputted by said FREQUENCY SYNTHESIZER MEANS; and

wherein said L2 TRACKER MEANS is fed from said L1 TRACKER MEANS by generated by said L1 TRACKER MEANS a W_L1.sbsb.--_F signal; and

wherein said L2 TRACKER MEANS is clocked by generated by said L1 TRACKER MEANS a DCLK signal, and

wherein said MICROPROCESSOR MEANS system is fed by output signals from said L1 TRACKER MEANS and said L2 TRACKER MEANS; and

wherein said L1 TRACKER MEANS and said L2 TRACKER MEANS are fed by a CONTROL signal from said MICROPROCESSOR MEANS.

10. The system of claim 9, wherein said L1 TRACKER MEANS for optimal tracking further comprises:

a CODE GENERATOR 1 MEANS for providing a locally generated replica of C/A code, and a locally generated replica of P code;

a MULTIPLEXER MEANS 1 connected to said CODE GENERATOR 1 MEANS for selecting a locally generated code C/A when Y code is ON and for selecting a locally generated P code when Y code is OFF, said MULTIPLEXER MEANS 1 being controlled by said MICROPROCESSOR MEANS system;

a carrier numerically controlled oscillator (CARRIER NCO MEANS

     1);

a CARRIER MIXER MEANS 1 connected to said CARRIER NCO MEANS 1 for multiplying outputted by said IF PROCESSOR MEANS digitized inphase IL1 and QL1 signals having carrier frequency with outputted by said CARRIER NCO MEANS 1 inphase and quadrature components of digital carrier;

wherein said CARRIER MIXER MEANS 1 outputs inphase IL1 and quadrature QL1 signals having zero carrier frequency;

a CODE MIXER MEANS 1 connected to said CARRIER MIXER MEANS 1, and connected to said MULTIPLEXER MEANS 1, for code correlating said CARRIER MIXER MEANS 1 output signals with said locally generated replica of C/A code or P-code;

wherein when said L1 TRACKER MEANS'"'"'s carrier tracking loop is closed via said CARRIER NCO MEANS 1 the input to said CODE MIXER MEANS 1 represents the satellite signal L1 C/A code; and

wherein said CODE MIXER MEANS 1 performs said code correlation at 3 time points (early, punctual and late) on the autocorrelation function graph creating an early, a punctual and a late sample of the autocorrelation function;

a block CORRELATORS MEANS 1 connected to said CODE MIXER MEANS 1 for integrating said early, punctual and late samples of said autocorrelation function over an integer multiple of EPOCH 1 signals;

wherein said CORRELATORS MEANS 1 output signal is fed to said MICROPROCESSOR MEANS system at a rate of L1 C/A code EPOCH 1, and wherein said MICROPROCESSOR MEANS uses said CORRELATORS MEANS 1 output signal to develop feedback signals for the L1 carrier tracking loop and for the L1 code tracking loop;

a code numerically controlled oscillator (CODE NCO 1 MEANS) connected to said block CORRELATORS MEANS 1 and connected to said CODE GENERATOR 1 MEANS for providing a signal at P-code rate for driving said CODE GENERATOR 1 MEANS, said CODE NCO 1 MEANS also providing a mechanism for aligning said locally generated replica of C/A code or P-code with said incoming satellite C/A code or P-code;

a CODE MIXER MEANS 2 connected to said CARRIER MIXER MEANS 1 and connected to said CODE GENERATOR 1 MEANS, said CARRIER MIXER MEANS 1 outputting in its Q channel an estimate of L1 Y code as an input to said CODE MIXER MEANS 2 when said L1 TRACKER is tracking L1 C/A code, said CODE GENERATOR MEANS outputting said local replica of known L1 P code as an input to said CODE MIXER MEANS 2, wherein said CODE MIXER MEANS 2 removes known L1 P code from said estimate of L1 Y code and outputs an estimate of L1 W code; and

a DIGITAL FILTER 1 MEANS connected to said CODE MIXER 2 MEANS for further processing said estimate of L1 W code outputted by said CODE MIXER 2, and wherein said DIGITAL FILTER 1 outputs a W_L1.sbsb.--_F signal for further processing by said L2 TRACKER MEANS block, and wherein said DIGITAL FILTER 1 outputs a DCLK clocking signal for clocking said L2 TRACKER MEANS block.

11. The system of claim 9, said L2 TRACKER MEANS further comprising:

a carrier numerically controlled oscillator (CARRIER NCO MEANS

     2);

a CARRIER MIXER MEANS 2 connected to said CARRIER NCO MEANS 2 for mixing outputted by said IF PROCESSOR MEANS digitized inphase I L2 and Q L2 signals having carrier frequency with outputted by said CARRIER NCO MEANS 2 inphase and quadrature components of digital carrier;

wherein said CARRIER MIXER MEANS 2 outputs inphase I L2 and quadrature Q L2 signals having zero carrier frequency; and

wherein when said L2 TRACKER is locked onto said L2 signal, said I output of said CARRIER MIXER 2 MEANS L2 represents an estimate of L2 Y code, and said Q output of said CARRIER MIXER 2 MEANS L2 contains no signal power;

a CODE NCO 2 MEANS, wherein said CODE NCO 2 is controlled by an L2 code tracking loop;

a CODE GENERATOR 2 MEANS connected to said CODE NCO 2, wherein said CODE NCO 2 drives said CODE GENERATOR 2 to produce a locally generated P code which is aligned with the incoming L2 satellite signal;

a CODE MIXER MEANS 3 connected to said CARRIER MIXER MEANS 2 and connected to said CODE GENERATOR 2 MEANS for code correlating said I and Q signals outputted by said CARRIER MIXER MEANS 2 with said P code outputted by said CODE GENERATOR 2;

wherein said CODE MIXER 3 removes said P code from said L2 Y code; and

wherein said CODE MIXER 3 develops six outputs (I_E ;

I_P ;

I_L ;

Q_E ;

Q_P ;

Q_L) which are correlations of said I and Q signals outputted by said CARRIER MIXER MEANS 2 with said P code outputted by said CODE GENERATOR 2 at three time points (early, punctual, and late); and

wherein when the encryption is OFF said six outputs (I_E ;

I_P ;

I_L ;

Q_E ;

Q_P ;

Q_L) are used for closing said L2 code and carrier tracking loops;

a DIGITAL FILTER 2 MEANS connected to said CODE MIXER 3 MEANS;

wherein said DIGITAL FILTER 2 MEANS is clocked by said DCLK signal outputted by said L1 TRACKER, and wherein said DIGITAL FILTER 2 MEANS outputs the filtered signals (I_E.sbsb.--_F ;

I_P.sbsb.--_F ;

I_L.sbsb.--_F ;

Q_E.sbsb.--_F ;

Q_P.sbsb.--_F ;

Q_L.sbsb.--_F) at different time points (early, punctual, and late) on the autocorrelation function of said incoming P(Y) code and said local P code generated by said CODE GENERATOR 2;

a CODE MIXER MEANS 4 connected to said DIGITAL FILTER 2 for mixing said (I_E.sbsb.--_F ;

I_P.sbsb.--_F ;

I_L.sbsb.--_F ;

Q_E.sbsb.--_F ;

Q_P.sbsb.--_F ;

Q_L.sbsb.--_F) signals outputted by said DIGITAL FILTER 2 with said W_L1.sbsb.--_F signal outputted by said DIGITAL FILTER 1; and

wherein said CODE MIXER MEANS 4 performs said code correlation at 3 time points (early, punctual and late) on the autocorrelation function graph creating an early, a punctual and a late sample of the autocorrelation function;

a MULTIPLEXER MEANS 2 connected to said CODE MIXER 4 MEANS and connected to said CODE MIXER 3 MEANS for selecting under the control of MICROPROCESSOR MEANS L2 P code correlation when the satellite is not encrypted, and optimal digital bandwidth compression L2 tracking when the satellite is encrypted; and

wherein when the satellite is not encrypted said MICROPROCESSOR MEANS selects the output of CODE MIXER 3 MEANS; and

wherein when the satellite is encrypted said MICROPROCESSOR MEANS selects the output of CODE MIXER 4 MEANS; and

a block CORRELATORS MEANS 2 connected to said MULTIPLEXER 2 MEANS for integrating said early, punctual and late samples of said autocorrelation function; and

wherein an output signal of said CORRELATORS 2 is fed to said MICROPROCESSOR SYSTEM at a rate of EPOCH 2; and

wherein said MICROPROCESSOR SYSTEM uses said CORRELATORS 2 MEANS output signal to develop feedback signals for the L2 carrier tracking loop and for the L2 code tracking loop.

12. The system of claim 10, wherein said CARRIER NCO MEANS 1 further comprises:

an n-bit ACCUMULATOR MEANS, n being an integer, for adding a new frequency word (B1 . . . Bn), B1 being the most significant bit (MSB), to a previous CARRIER NCO MEANS 1 output frequency word (Q1 . . . Qn) on each sample clock, wherein said ACCUMULATOR MEANS is caused to overflow periodically at the predetermined output frequency;

a first LATCH MEANS 1 connected to said ACCUMULATOR MEANS for latching in said new frequency word B1 . . . Bn under the control signal of said MICROPROCESSOR MEANS, wherein L-top bits of said ACCUMULATOR MEANS output wave are used as said CARRIER NCO MEANS 1 (I) output wave;

L being an integer, L being less than n, L being greater or equal to 1; and

wherein when the carrier tracking loop is locked L-top bits of said CARRIER NCO MEANS 1 output wave are used as the inphase version (I) of the carrier signal L1 which is phase locked with the satellite signal;

a first ADDER MEANS 1 for adding (01) to the 2-top bits (S1 S2) of the CARRIER NCO MEANS 1 output (S1 . . . Sn) frequency word to obtain 2-top bits (R1 R2);

a third LATCH MEANS 3 connected to said first ADDER MEANS 1 for generating a quadrature version Q of carrier signal L1 by clocking in at the rate of SCLK signal said 2-top bits (R1 R2); and

wherein said LATCH MEANS 3 generates said QL1 signal in the form of L-bit word (R1 R2 S3 . . . SL);

a second LATCH MEANS 2 connected to said ACCUMULATOR MEANS for latching top m bits (C1 . . . Cm), m being an integer (m<

n), of the CARRIER NCO MEANS 1 output signal on the edge of the MSEC timing signal, wherein said (C1 . . . Cm) signal represents a carrier phase measurement signal.

13. The system of claim 12, wherein said n-bit ACCUMULATOR MEANS with said L-bit output wave further comprises:

a second ADDER MEANS 2 connected to said first LATCH MEANS 1 for adding a frequency word (B1 . . . Bn), B1 being the most significant bit (MSB), to a previous CARRIER NCO MEANS 1 frequency output (Q1 . . . Qn) on each sample clock; and

a fourth LATCH MEANS 4 connected to said second ADDER MEANS 2 for generating said output CARRIER NCO MEANS 1 signal (Q1 . . . Qn), wherein said fourth LATCH MEANS 4 is caused to overflow at the desired output frequency, and wherein L-top output bits of said fourth LATCH MEANS are used as said CARRIER NCO MEANS 1 output signal.

14. The system of claim 11, wherein said CARRIER NCO MEANS 2 further comprises:

an n-bit ACCUMULATOR MEANS, n being an integer, for adding a new frequency word (B1 . . . Bn), B1 being the most significant bit (MSB), to a previous CARRIER NCO MEANS 2 output frequency word (Q1 . . . Qn) on each sample clock, wherein said ACCUMULATOR MEANS is caused to overflow periodically at the predetermined output frequency;

a first LATCH MEANS 1 connected to said ACCUMULATOR MEANS for latching in said new frequency word B1 . . . Bn under the control signal of said MICROPROCESSOR MEANS, wherein L-top bits of said ACCUMULATOR MEANS output wave are used as said CARRIER NCO MEANS 2 (I) output wave;

L being an integer, L being less than n, L being greater or equal to 1; and

wherein when the carrier tracking loop is locked L-top bits of said CARRIER NCO MEANS 2 output wave are used as the inphase version (I) of the carrier signal L2 which is phase locked with the satellite signal;

a first ADDER MEANS 1 for adding (01) to the 2-top bits (S1 S2) of the CARRIER NCO MEANS 2 output (S1 . . . Sn) frequency word to obtain 2-top bits (R1 R2);

a third LATCH MEANS 3 connected to said first ADDER MEANS 1 for generating a quadrature version Q of carrier signal L2 by clocking in at the rate of SCLK signal said 2-top bits (R1 R2); and

wherein said LATCH MEANS 3 generates said QL2 signal in the form of L-bit word (R1 R2 S3 . . . SL);

a second LATCH MEANS 2 connected to said ACCUMULATOR MEANS for latching top m bits (C1 . . . Cm) of the CARRIER NCO MEANS 1 output signal on the edge of the MSEC timing signal, m being an integer, m being less than n;

wherein said (C1 . . . Cm) signal represents a carrier phase measurement signal.

15. The system of claim 14, wherein said n-bit ACCUMULATOR MEANS with said L-bit output wave further comprises:

a second ADDER MEANS 2 connected to said first LATCH MEANS 1 for adding a frequency word (B1 . . . Bn), B1 being the most significant bit (MSB), to a previous CARRIER NCO MEANS 2 frequency output (Q1 . . . Qn) on each sample clock; and

a fourth LATCH MEANS 4 connected to said second ADDER MEANS 2 for generating said output CARRIER NCO MEANS 2 signal (Q1 . . . Qn), wherein said fourth LATCH MEANS 4 is caused to overflow at the desired output frequency and wherein L-top output bits of said fourth LATCH MEANS are used as said CARRIER NCO MEANS 2 output signal.

16. The system of claim 10, wherein said CARRIER MIXER MEANS 1 further comprises:

a first MULTIPLIER MEANS 1, wherein said first MULTIPLIER MEANS 1 performs a multiplication operation of L-bits of IL1 satellite carrier signal and M-bits of inphase version I of carrier frequency, and wherein said first MULTIPLIER MEANS 1 outputs a (IL1)*I signal;

a second MULTIPLIER MEANS 2, wherein said second MULTIPLIER MEANS 2 performs a multiplication operation of L-bits of QL1 satellite carrier signal and M-bits of quadrature version Q of carrier frequency, and wherein said second MULTIPLIER MEANS 2 outputs a (QL1)*Q signal;

a first ADDER MEANS 1 connected to said first MULTIPLIER MEANS 1 and connected to said second MULTIPLIER MEANS 2 for subtracting said (QL1)*Q signal from said (IL1)*I signal;

a third MULTIPLIER MEANS 3, wherein said third MULTIPLIER MEANS 3 performs a multiplication operation of L-bits of IL1 satellite carrier signal and M-bits of quadrature version Q of carrier frequency, and wherein said third MULTIPLIER MEANS 3 outputs a (IL1)*Q signal;

a fourth MULTIPLIER MEANS 4, wherein said fourth MULTIPLIER MEANS 4 performs a multiplication operation of L-bits of QL1 satellite carrier signal and M-bits of inphase version I of carrier frequency, and wherein said fourth MULTIPLIER MEANS 4 outputs a (QL1)*I signal; and

a second ADDER MEANS 2 connected to said third MULTIPLIER MEANS 3 and connected to said fourth MULTIPLIER MEANS 4 for adding said (QL1)*I signal to said (IL1)*Q signal.

17. The system of claim 11, wherein said CARRIER MIXER MEANS 2 further comprises:

a first MULTIPLIER MEANS 1, wherein said first MULTIPLIER MEANS 1 performs a multiplication operation of M-bits of IL2 satellite carrier signal and L-bits of inphase version I of carrier frequency, and wherein said first MULTIPLIER MEANS 1 outputs a (IL2)*I signal;

a second MULTIPLIER MEANS 2, wherein said second MULTIPLIER MEANS 2 performs a multiplication operation of M-bits of QL2 satellite carrier signal and L-bits of quadrature version Q of carrier frequency, and wherein said second MULTIPLIER MEANS 2 outputs a (QL2)*Q signal;

a first ADDER MEANS 1 connected to said first MULTIPLIER MEANS 1 and connected to said second MULTIPLIER MEANS 2 for subtracting said (QL2)*Q signal from said (IL2)*I signal;

a third MULTIPLIER MEANS 3, wherein said third MULTIPLIER MEANS 3 performs a multiplication operation of M-bits of IL2 satellite carrier signal and L-bits of quadrature version Q of carrier frequency, and wherein said third MULTIPLIER MEANS 3 outputs a (IL2)*Q signal;

a fourth MULTIPLIER MEANS 4, wherein said fourth MULTIPLIER MEANS 4 performs a multiplication operation of M-bits of QL2 satellite carrier signal and L-bits of inphase version I of carrier frequency, and wherein said fourth MULTIPLIER MEANS 4 outputs a (QL2)*I signal; and

a second ADDER MEANS 2 connected to said third MULTIPLIER MEANS 3 and connected to said fourth MULTIPLIER MEANS 4 for adding said (QL2)*I signal to said (IL2)*Q signal.

18. The system of claim 10, wherein said CODE MIXER MEANS 1 further comprises:

a first MULTIPLIER MEANS 1 for multiplying said incoming I signal with an early version (E) of said local C/A code or P-code;

a second MULTIPLIER MEANS 2 for multiplying said incoming I signal with a punctual version (P) of said local C/A code or P-code;

a third MULTIPLIER MEANS 3 for multiplying said incoming I signal with a late version (L) of said local C/A code or P-code;

a fourth MULTIPLIER MEANS 4 for multiplying said incoming Q signal with an early version (E) of said local C/A code or P-code;

a fifth MULTIPLIER MEANS 5 for multiplying said incoming Q signal with a punctual version (P) of said local C/A code or P-code; and

a sixth MULTIPLIER MEANS 6 for multiplying said incoming Q signal with a late version (L) of said local C/A code or P-code.

19. The system of claim 10, wherein said CODE MIXER MEANS 2 further comprises:

a MULTIPLIER MEANS for multiplying said incoming L1Y code estimate with said locally generated LiP code, wherein said MULTIPLIER MEANS outputs an L1W code estimate.

20. The system of claim 11, wherein said CODE MIXER MEANS 3 further comprises:

a first MULTIPLIER MEANS 1 for multiplying M-bit of said I estimate of the incoming satellite L2 code at early time point (E) on the autocorrelation function graph with said locally generated L2 P code;

said first MULTIPLIER MEANS creating an early I_E correlation;

a second MULTIPLIER MEANS 2 for multiplying M-bit of said I estimate of the incoming satellite L2 code at punctual time point (P) on the autocorrelation function graph with said locally generated L2 P code;

said second MULTIPLIER MEANS creating a punctual I_P correlation;

a third MULTIPLIER MEANS 3 for multiplying M-bit of said I estimate of the incoming satellite L2 code at late time point (L) on the autocorrelation function graph with said locally generated L2 P code;

said third MULTIPLIER MEANS 3 creating a late I_L correlation;

a fourth MULTIPLIER MEANS 4 for multiplying M-bit of said Q estimate of the incoming satellite L2 code at early time point (E) on the autocorrelation function graph with said locally generated L2 P code;

said fourth MULTIPLIER MEANS 4 creating an early Q_E correlation;

a fifth MULTIPLIER MEANS 5 for multiplying M-bit of said Q estimate of the incoming satellite L2 code at punctual time point (P) on the autocorrelation function graph with said locally generated L2 P code;

said fifth MULTIPLIER MEANS 5 creating a punctual Q_P correlation; and

a sixth MULTIPLIER MEANS 6 for multiplying M-bit of said Q estimate of the incoming satellite L2 code at late time point (L) on the autocorrelation function graph with said locally generated L2 P code;

said sixth MULTIPLIER MEANS 6 creating a late Q_L correlation.

21. The system of claim 11, wherein said CODE MIXER MEANS 4 is designed for mixing the L2 time delayed signals (I_E.sbsb.--_F ;

I_P.sbsb.--_F ;

I_L.sbsb.--_F ;

Q_E.sbsb.--_F ;

Q_P.sbsb.--_F ; and

Q_L.sbsb.--_F) with the estimated L1 W-code energy (W_L1.sbsb.--_F);

said CODE MIXER 4 further comprising;

a first MULTIPLIER MEANS 1 for multiplying said I_E.sbsb.--_F signal with said W_L1.sbsb.--_F signal, said first MULTIPLIER 1 outputting E-early with respect to the P code autocorrelation function correlations of the IL2 signal I_EW.sbsb.--_F ;

a second MULTIPLIER MEANS 2 for multiplying said I_P.sbsb.--_F signal with said W_L1.sbsb.--_F signal, said second MULTIPLIER 2 outputting P-punctual with respect to the P code autocorrelation function correlations of the IL2 signal I_PW.sbsb.--_F ;

a third MULTIPLIER MEANS 3 for multiplying said I_L.sbsb.--_F signal with said W_L1.sbsb.--_F signal, said third MULTIPLIER 3 outputting L-late with respect to the P code autocorrelation function correlations of the IL2 signal I_LW.sbsb.--_F ;

a fourth MULTIPLIER MEANS 4 for multiplying said Q_E.sbsb.--_F signal with said W_L1.sbsb.--_F signal, said fourth MULTIPLIER 4 outputting E-early with respect to the P code autocorrelation function correlations of the QL2 signal Q_EW.sbsb.--_F ;

a fifth MULTIPLIER MEANS 5 for multiplying said Q_P.sbsb.--_F signal with said W_L1.sbsb.--_F signal, said fifth MULTIPLIER 5 outputting P-punctual with respect to the P code autocorrelation function correlations of the QL2 signal Q_PW.sbsb.--_F ;

a sixth MULTIPLIER MEANS 6 for multiplying said Q_L.sbsb.--_F signal with said W_L1.sbsb.--_F signal, said sixth MULTIPLIER 6 outputting L-late with respect to the P code autocorrelation function correlations of the QL2 signal Q_LW.sbsb.--_F.

22. The system of claim 10, wherein said CODE GENERATOR 1 MEANS further comprises:

a first DIVIDING MEANS for dividing an input signal from said CODE NCO 1 MEANS to provide a C/A CODE GENERATOR MEANS clock signal;

a C/A CODE GENERATOR MEANS connected to said first DIVIDING MEANS for generating a C/A code signal and an EPOCH 1 signal under the CONTROL signal of said MICROPROCESSOR MEANS, wherein said C/A code signal is the locally generated C/A code, and wherein said EPOCH 1 signal is the repetition rate of said C/A code, and wherein said C/A CODE GENERATOR can be adjusted under said CONTROL signal to generate a particular satellite'"'"'s C/A code; and

a P CODE GENERATOR MEANS connected to said CODE NCO 1 MEANS, wherein said P CODE GENERATOR MEANS is clocked by said CODE NCO 1 MEANS signal under the CONTROL signal of said MICROPROCESSOR MEANS, and wherein said P CODE GENERATOR generates a P-code signal, and wherein said P CODE GENERATOR can be adjusted under said CONTROL signal to generate a particular satellite'"'"'s P code.

23. The system of claim 11, wherein said CODE GENERATOR 2 MEANS further comprises:

a first DIVIDING MEANS for dividing an input signal from said CODE NCO 2 MEANS to provide a C/A CODE GENERATOR MEANS clock signal;

a C/A CODE GENERATOR MEANS connected to said first DIVIDING MEANS for generating an EPOCH 2 signal under the CONTROL signal of said MICROPROCESSOR MEANS, and wherein said EPOCH 2 signal is used as one of said CORRELATORS 2 block control signals; and

a P CODE GENERATOR MEANS connected to said CODE NCO 2 MEANS, wherein said P CODE GENERATOR MEANS is docked by said CODE NCO 2 MEANS signal under the CONTROL signal of said MICROPROCESSOR MEANS, and wherein said P CODE GENERATOR generates a P-code signal, and wherein said P CODE GENERATOR can be adjusted under said CONTROL signal to generate a particular satellite'"'"'s P code.

24. The system of claim 10,

wherein said block CORRELATORS MEANS 1 is used for integrating said IE (inphase early), said IP (inphase punctual), said IL (inphase late), said QE (quadrature early), said QP (quadrature punctual), and said QL (quadrature late) versions of the correlated samples of said L1 C/A (or P) code with said locally generated version of C/A (or P) code across a time period given by a multiple of L1 C/A EPOCH 1;

and

wherein said IE, IL, QE, and QL are used by said code tracking loop by forming;

a code phase estimate=KI(IE-IL), when said carrier loop is locked;

or

a code phase estimate=K1[(IE² +QE²)^1/2 -(IL² +QL²)^1/2 ], when said carrier loop is not locked;

where K1 is a L1 code loop gain factor; and

wherein said IP, and QP are used by said carrier tracking loop by forming;

a carrier phase estimate=arctan(QP/IP);

said block CORRELATORS MEANS 1 further comprising;

a first UP/DOWN COUNTER MEANS 1 for integrating said IE across a period defined by said C/A EPOCH 1 signal;

wherein said UP/DOWN COUNTER MEANS 1 adds if the input is positive and subtracts if it is negative and is reset on EPOCH 1; and

a first LATCH MEANS 1 connected to said first UP/DOWN COUNTER MEANS 1 for reading by said MICROPROCESSOR MEANS system said IE signal integrated by said UP/DOWN COUNTER MEANS 1;

a second UP/DOWN COUNTER MEANS 2 for integrating said IP across a period defined by said C/A EPOCH 1 signal;

wherein said UP/DOWN COUNTER MEANS 2 adds if the input is positive and subtracts if it is negative and is reset on EPOCH 1; and

a second LATCH MEANS 2 connected to said second UP/DOWN COUNTER MEANS 2 for reading by said MICROPROCESSOR MEANS system said IP signal integrated by said UP/DOWN COUNTER MEANS 2;

a third UP/DOWN COUNTER MEANS 3 for integrating said IL signal across a period defined by said C/A EPOCH 1 signal;

wherein said UP/DOWN COUNTER MEANS 3 adds if the input is positive and subtracts if it is negative and is reset on EPOCH 1; and

a third LATCH MEANS 3 connected to said third UP/DOWN COUNTER MEANS 3 for reading by said MICROPROCESSOR MEANS system said IL signal integrated by said UP/DOWN COUNTER MEANS 3;

a fourth UP/DOWN COUNTER MEANS 4 for integrating said QE signal across a period defined by said C/A EPOCH 1 signal;

wherein said UP/DOWN COUNTER MEANS 4 adds if the input is positive and subtracts if it is negative and is reset on EPOCH 1; and

a fourth LATCH MEANS 4 connected to said fourth UP/DOWN COUNTER MEANS 4 for reading by said MICROPROCESSOR MEANS system said QE signal integrated by said UP/DOWN COUNTER MEANS 4;

a fifth UP/DOWN COUNTER MEANS 5 for integrating said QP signal across a period defined by said C/A EPOCH 1 signal;

wherein said UP/DOWN COUNTER MEANS 5 adds if the input is positive and subtracts if it is negative and is reset on EPOCH 1; and

a fifth LATCH MEANS connected to said fifth UP/DOWN COUNTER MEANS 5 for reading by said MICROPROCESSOR MEANS system said QP signal integrated by said UP/DOWN COUNTER MEANS 5;

a sixth UP/DOWN COUNTER MEANS 6 for integrating said QL across a period defined by said C/A EPOCH 1 signal;

wherein said UP/DOWN COUNTER MEANS 6 adds if the input is positive and subtracts if it is negative and is reset on EPOCH 1; and

a sixth LATCH MEANS 6 connected to said sixth UP/DOWN COUNTER MEANS 6 for reading by said MICROPROCESSOR MEANS system said QL signal integrated by said UP/DOWN COUNTER MEANS 6.

25. The system of claim 11,

wherein said block CORRELATORS MEANS 2 accumulates the result of L2 P code correlation when the satellite is not encrypted, and accumulates the result of the optimal digital bandwidth compression L2 tracking when the satellite is encrypted;

and wherein said block CORRELATORS MEANS 2 is used for integrating said IE (inphase early), said IP (inphase punctual), said IL (inphase late), said QE (quadrature early), said QP (quadrature punctual), and said QL (quadrature late) version of the L2 code across a time period given by said EPOCH 2 signal; and

wherein said IE, IL, QE, and QL are used by said code tracking loop by forming;

a code phase estimate=K2(IE-IL), when said carrier loop is locked;

or

a code phase estimate=K2[(IE² +QE²)^1/2 -(IL² +QL²)^1/2 ], when said carrier loop is not locked;

K2 being an L2-code loop gain factor; and

wherein said PQ, and PI codes are used by said carrier tracking loop by forming;

a carrier phase estimate=arctan(PQ/PI);

said block CORRELATORS MEANS 2 further comprising;

a first UP/DOWN COUNTER MEANS 1 for integrating said IE signal across a period defined by said EPOCH 2 signal;

wherein said UP/DOWN COUNTER MEANS 1 adds if the input is positive and subtracts if it is negative and is reset on EPOCH 2 signal; and

wherein when the satellite is encrypted said UP/DOWN COUNTER MEANS 1 accumulates on each edge of said DCLK signal; and

wherein when the satellite is not encrypted said UP/DOWN COUNTER MEANS 1 accumulates on each edge of said SCLK signal;

a first LATCH MEANS 1 connected to said first UP/DOWN COUNTER MEANS 1 for reading by said MICROPROCESSOR MEANS system via said MULTIPLEXER 3 block said IE signal integrated by said UP/DOWN COUNTER MEANS 1 at a rate of EPOCH 2 signal;

a second UP/DOWN COUNTER MEANS 2 for integrating said IP signal across a period defined by said EPOCH 2 signal;

wherein said UP/DOWN COUNTER MEANS 2 adds if the input is positive and subtracts if it is negative and is reset on EPOCH 2 signal; and

wherein when the satellite is encrypted said UP/DOWN COUNTER MEANS 2 accumulates on each edge of said DCLK signal; and

wherein when the satellite is not encrypted said UP/DOWN COUNTER MEANS 2 accumulates on each edge of said SCLK signal;

a second LATCH MEANS 2 connected to said second UP/DOWN COUNTER MEANS 2 for reading by said MICROPROCESSOR MEANS system via said MULTIPLEXER 3 block said IP signal integrated by said UP/DOWN COUNTER MEANS 2 at a rate of EPOCH 2 signal;

a third UP/DOWN COUNTER MEANS 3 for integrating said IL signal across a period defined by said EPOCH 2 signal;

wherein said UP/DOWN COUNTER MEANS 3 adds if the input is positive and subtracts if it is negative and is reset on EPOCH 2 signal; and

wherein when the satellite is encrypted said UP/DOWN COUNTER MEANS 3 accumulates on each edge of said DCLK signal; and

wherein when the satellite is not encrypted said UP/DOWN COUNTER MEANS 3 accumulates on each edge of said SCLK signal;

a third LATCH MEANS 3 connected to said third UP/DOWN COUNTER MEANS 3 for reading by said MICROPROCESSOR MEANS system via said MULTIPLEXER 3 block said IL signal integrated by said UP/DOWN COUNTER MEANS 3 at a rate of EPOCH 2 signal;

a fourth UP/DOWN COUNTER MEANS 4 for integrating said QE signal across a period defined by said EPOCH 2 signal;

wherein said UP/DOWN COUNTER MEANS 4 adds if the input is positive and subtracts if it is negative and is reset on EPOCH 2 signal; and

wherein when the satellite is encrypted said UP/DOWN COUNTER MEANS 4 accumulates on each edge of said DCLK signal; and

wherein when the satellite is not encrypted said UP/DOWN COUNTER MEANS 4 accumulates on each edge of said SCLK signal;

a fourth LATCH MEANS 4 connected to said fourth UP/DOWN COUNTER MEANS 4 for reading by said MICROPROCESSOR MEANS system via said MULTIPLEXER 3 block said QE signal integrated by said UP/DOWN COUNTER MEANS 4 at a rate of EPOCH 2 signal;

a fifth UP/DOWN COUNTER MEANS 5 for integrating said QP signal across a period defined by said EPOCH 2 signal;

wherein said UP/DOWN COUNTER MEANS 5 adds if the input is positive and subtracts if it is negative and is reset on EPOCH 2 signal; and

wherein when the satellite is encrypted said UP/DOWN COUNTER MEANS 5 accumulates on each edge of said DCLK signal; and

wherein when the satellite is not encrypted said UP/DOWN COUNTER MEANS 5 accumulates on each edge of said SCLK signal;

a fifth LATCH MEANS 5 connected to said fifth UP/DOWN COUNTER MEANS 5 for reading by said MICROPROCESSOR MEANS system via said MULTIPLEXER 3 block said QP signal integrated by said UP/DOWN COUNTER MEANS 5 at a rate of EPOCH 2 signal;

a sixth UP/DOWN COUNTER MEANS 6 for integrating said IE across a period defined by said EPOCH 2 signal;

wherein said UP/DOWN COUNTER MEANS 6 adds if the input is positive and subtracts if it is negative and is reset on EPOCH 2; and

wherein when the satellite is encrypted said UP/DOWN COUNTER MEANS 6 accumulates on each edge of said DCLK signal; and

wherein when the satellite is not encrypted said UP/DOWN COUNTER MEANS 6 accumulates on each edge of said SCLK signal;

a sixth LATCH MEANS 6 connected to said sixth UP/DOWN COUNTER MEANS 6 for reading by said MICROPROCESSOR MEANS system via said MULTIPLEXER 3 block said QL signal integrated by said UP/DOWN COUNTER MEANS 6 at a rate of EPOCH 2 signal.

26. The system of claim 10, wherein said CODE NCO 1 MEANS provides a clock for said CODE GENERATOR 1 MEANS which generates said locally generated replica of C/A code and P code;

said CODE NCO 1 MEANS further comprising;

a n-bit ADDER MEANS, n being an integer;

an n-bit LATCH MEANS; and

a MULTIPLEXER MEANS connected to said n-bit ADDER MEANS;

wherein on each sample clock edge the output of said LATCH MEANS is added to the output of said MULTIPLEXER MEANS by said ADDER MEANS; and

wherein said MULTIPLEXER MEANS outputs one of three n-bit values (N, M or SHIFT); and

wherein said CODE NCO 1 MEANS under normal operation outputs;

CODE NCO 1 MEANS frequency=(N×

SCLK)/(2ⁿ -M+N); and

wherein said CODE NCO 1 MEANS under code phase shift operation outputs;

code phase shift=(M-SHIFT)/(2ⁿ -M+N).

27. The system of claim 10, wherein said CODE NCO 1 MEANS provides a clock for said CODE GENERATOR 1 MEANS which generates said locally generated replica of C/A code and P code;

said CODE NCO 1 MEANS further comprising;

a 12-bit ADDER MEANS;

a 12-bit LATCH MEANS connected to said 12-bit ADDER MEANS; and

a MULTIPLEXER MEANS connected to said 12-bit ADDER MEANS;

wherein on each sample clock edge the output of said LATCH MEANS is added to the output of said MULTIPLEXER MEANS by said ADDER MEANS; and

wherein said MULTIPLEXER MEANS outputs one of three 12-bit values (N=1023, M=2619, or SHIFT); and

wherein said CODE NCO 1 MEANS under normal operation outputs;

CODE NCO 1 MEANS frequency=10.23 MHz;

and wherein said CODE NCO 1 MEANS under code phase shift operation outputs;

code phase shift=(2619-SHIFT)/2500 sample clocks.

28. The system of claim 11, wherein said CODE NCO 2 MEANS provides a clock for said CODE GENERATOR 2 MEANS which generates said locally generated replica of P code;

said CODE NCO 2 MEANS further comprising;

an n-bit ADDER MEANS, n being an integer;

an n-bit LATCH MEANS connected to said n-bit ADDER MEANS; and

a MULTIPLEXER MEANS connected to said n-bit ADDER MEANS;

wherein on each sample clock edge the output of said LATCH MEANS is added to the output of said MULTIPLEXER MEANS by said ADDER MEANS; and

wherein said MULTIPLEXER MEANS outputs one of three n-bit values (N, M or SHIFT); and

wherein said CODE NCO 2 MEANS under normal operation outputs;

CODE NCO 2 MEANS frequency=(N×

SCLK)/(2ⁿ -M+N);

and wherein said CODE NCO 2 MEANS under code phase shift operation outputs;

code phase shift=(M-SHIFT)/(2ⁿ -M+N).

29. The system of claim 11, wherein said CODE NCO 2 MEANS provides a clock for said CODE GENERATOR 2 MEANS which generates said locally generated replica of P code;

said CODE NCO 2 MEANS further comprising;

a 12-bit ADDER MEANS;

a 12-bit LATCH MEANS connected to said 12-bit ADDER MEANS; and

a MULTIPLEXER MEANS connected to said 12-bit ADDER MEANS;

wherein on each sample clock edge the output of said LATCH MEANS is added to the output of said MULTIPLEXER MEANS by said ADDER MEANS; and

wherein said MULTIPLEXER MEANS outputs one of three 12-bit values (N=1023, M=2619, or SHIFT); and

wherein said CODE NCO 2 MEANS under normal operation outputs;

CODE NCO 2 MEANS frequency=10.23 MHz;

and wherein said CODE NCO 2 MEANS under code phase shift operation outputs;

code phase shift=(2619-SHIFT)/2500 sample clocks.

30. The system of claim 10, wherein said DIGITAL FILTER MEANS 1 further comprises:

an L-bit SHIFT REGISTER MEANS (W1,W2, . . . Wx), X being an integer, for making an X-number of delayed copies of said estimate of L1 W code, wherein a first copy L1 W1-code is delayed by one sample clock (SCLK), a second copy L1 W2-code is delayed by two sample clocks (2 SCLK), an (i) copy L1 Wi is delayed by (i SCLK) sample clocks, i being an integer, and an x-copy L1 Wx-code is delayed by (x SCLK) sample clocks;

an X-number of MULTIPLIER MEANS (C1, . . . Cx), wherein a first MULTIPLIER MEANS C1 transforms said first L1 W1-code into a L1 C1W1-code, wherein a second MULTIPLIER MEANS C2 transforms said second L1 W2-code into a L1 C2W2-code, and wherein an (i) MULTIPLIER MEANS Ci transform said L1 Wi-code into a L1 CiWi code, and wherein an (x) MULTIPLIER MEANS transforms said L1 Wx-code into a L1 CxWx-code;

an ADDER MEANS connected to each of said Ci MULTIPLIER MEANS for adding each said L1 CiWi-codes into a signal C1W1+C2W2+ . . . CxWx;

a DIVIDE BY K MEANS for dividing said SCLK signal by K for generating said DCLK clocking signal, K being an integer; and

a LATCH connected to said ADDER for latching in said C1W1+C2W2+ . . . CxWx signal at the rate of said DCLK clock for generating an output signal W_L1.sbsb.--_F.

31. The system of claim 10, wherein said DIGITAL FILTER MEANS 1 further comprises a finite impulse response (FIR) DIGITAL FILTER 1;

and wherein said FIR DIGITAL FILTER 1 performs the optimal tracking operation by matching the observed W-code spectrum and by optimizing the signal-to-noise (SNR) ratio of the cross-correlation process.

32. The system of claim 31, wherein said FIR DIGITAL FILTER 1 is implemented using a direct form transfer function.

33. The system of claim 31, wherein said FIR DIGITAL FILTER 1 is implemented using a cascade form transfer function.

34. The system of claim 31, wherein said FIR DIGITAL FILTER 1 is implemented using a parallel form transfer function.

35. The system of claim 10, wherein said DIGITAL FILTER MEANS 1 further comprises an infinite impulse response (IIR) DIGITAL FILTER 1;

and wherein said IIR DIGITAL FILTER 1 performs the optimal tracking operation by matching the observed W-code spectrum and by optimizing the signal-to-noise (SNR) ratio of the cross-correlation process.

36. The system of claim 35, wherein said IIR DIGITAL FILTER 1 is implemented using a direct form transfer function.

37. The system of claim 35, wherein said IIR DIGITAL FILTER 1 is implemented using a cascade form transfer function.

38. The system of claim 35, wherein said IIR DIGITAL FILTER 1 is implemented using a parallel form transfer function.

39. The system of claim 31, wherein said FIR DIGITAL FILTER 1 further comprises

a first L-bit SHIFT REGISTER MEANS (X1,X2, . . . Xm), m being an integer, for making an m-number of delayed copies of an input signal X, wherein said input signal X comprises said I estimate of L1 W code, wherein a first copy of said input signal X1 is delayed by one sample clock SCLK, a second copy of said input signal X2 is delayed by two sample clocks, an (i) copy of said input signal Xi is delayed by (i) sample clocks, i being an integer, and an m-copy of said input signal Xm is delayed by (m) sample clocks;

an m-number of MULTIPLIER MEANS (C1, . . . Cm), wherein a first MULTIPLIER MEANS C1 transforms said X1 signal into a C1X1 signal; and

wherein a second MULTIPLIER MEANS C2 transforms said X2 signal into a C2X2 signal, and wherein an (i) MULTIPLIER MEANS Ci transform said Xi signal into a CiXi signal, and wherein an (m) MULTIPLIER MEANS transforms said Xm signal into a CmXm signal;

and an ADDER MEANS connected to each of said Ci MULTIPLIER MEANS for adding each said CiXi signals into an output function Yout, wherein said output function Your is equal to;

Yout=C1X1+C2X2+ . . . CmXm;

wherein said FIR DIGITAL FILTER MEANS 1 optimizes the signal-to-noise ratio by adapting to changes in the input signal X frequency spectrum.

40. The system of claim 35, wherein said IIR DIGITAL FILTER 1 further comprises

a first L-bit SHIFT REGISTER MEANS (X1,X2, . . . Xm), m being an integer, for making an m-number of delayed copies of an input signal Xinput, wherein a first copy of said input signal X1 is delayed by one sample clock SCLK, a second copy of said input signal X2 is delayed by two sample clocks, an (i) copy of said input signal Xi is delayed by (i) sample clocks, i being an integer, and an m-copy of said input signal Xm is delayed by (m) sample clocks;

an m-number of MULTIPLIER MEANS (C1, . . . Cm), wherein a first MULTIPLIER MEANS C1 transforms said X1 signal into a C1X1 signal; and

wherein a second MULTIPLIER MEANS C2 transforms said X2 signal into a C2X2 signal, and wherein an (i) MULTIPLIER MEANS Ci transform said Xi signal into a CiXi signal, and wherein an (m) MULTIPLIER MEANS transforms said Xm signal into a CmXm signal;

a second L-bit SHIFT REGISTER MEANS (Y1,Y2, . . . Yn), n being an integer, for making an n-number of delayed copies of an output signal Y, and wherein a first copy of said output signal Y1 is delayed by one sample clock SCLK, a second copy of said output signal Y2 is delayed by two sample clocks, an (i) copy of said output signal Yi is delayed by (i) sample clocks, i being an integer, and an n-copy of said output signal Yn is delayed by (n) sample clocks;

an n-number of MULTIPLIER MEANS (B1, . . . Bn), wherein a first MULTIPLIER MEANS B1 transforms said Y1 signal into a B1Y1 signal; and

wherein a second MULTIPLIER MEANS B2 transforms said Y2 signal into a B2Y2 signal, and wherein an (i) MULTIPLIER MEANS Bi transform said Yi signal into a BiYi signal, and wherein an (n) MULTIPLIER MEANS Bn transforms said Ym signal into a BnYn signal;

and an ADDER MEANS connected to each of said Ci and Bi MULTIPLIER MEANS for adding each said CiXi and BiYi signals into an output function Yout, wherein said output function Yout is equal to;

Yout=C1X1+C2X2+ . . . +CmXm+B1Y1+B2Y2+ . . . +BnYn;

and wherein said IIR DIGITAL FILTER MEANS 1 optimizes the signal-to-noise ratio by adapting to changes in the input signal X frequency spectrum.

41. The system of claim 11, wherein said DIGITAL FILTER 2 further comprises:

a DIGITAL FILTER X1 block filtering said I component of L2 W code early estimate I_E and outputting a filtered signal I_E.sbsb.--_F at a rate DCLK;

a DIGITAL FILTER X2 block filtering said I component of L2 W code punctual estimate I_P and outputting a filtered signal I_P.sbsb.--_F at a rate DCLK;

a DIGITAL FILTER X3 block filtering said I component of L2 W code late estimate I_L and outputting a filtered signal I_L.sbsb.--_F at a rate DCLK;

a DIGITAL FILTER X4 block filtering said Q component of L2 W code early estimate Q_E and outputting a filtered signal Q_E.sbsb.--_F at a rate DCLK;

a DIGITAL FILTER X5 block filtering said Q component of L2 W code punctual estimate Q_P and outputting a filtered signal Q_P.sbsb.--_F at a rate DCLK; and

a DIGITAL FILTER X6 block filtering said Q component of L2 W code late estimate Q_L and outputting a filtered signal Q_L.sbsb.--_F at a rate DCLK.

42. The system of claim 41, wherein said DIGITAL FILTER X further comprises

a first L-bit SHIFT REGISTER MEANS (W1,W2, . . . Wx), X being an integer, for making an X-number of delayed copies of said I estimate of L2 W code, wherein a first copy of I estimate of L2 W1-code is delayed by one sample clock, a second copy of I estimate of L2 W2-code is delayed by two sample clocks, an (i) copy of I estimate of L2 Wi is delayed by (i) sample clocks, i being an integer, and an x-copy of I estimate of L2 Wx-code is delayed by (x) sample clocks;

an X-number of MULTIPLIER MEANS (C1, . . . Cx), wherein a first MULTIPLIER MEANS C1 transforms said first I estimate of L2 W1-code into a L2 C1W1-code, wherein a second MULTIPLIER MEANS C2 transforms said second I estimate of L2 W2-code into a L2 C2W2-code, and wherein an (i) MULTIPLIER MEANS Ci transform said I estimate of L2 Wi-code into a L2 CiWi code, and wherein an (x) MULTIPLIER MEANS transforms said I estimate of L2 Wx-code into an L2 CxWx-code;

an ADDER MEANS connected to each of said Ci MULTIPLIER MEANS for adding each said L2 CiWi-codes into a C1W1+C2W2+ . . . CxWx signal; and

a FLIP-FLOP MEANS connected to said ADDER MEANS for generating an output signal OUTPUT;

wherein said LATCH is clocked by said DCLK signal.

43. The system of claim 11, wherein said DIGITAL FILTER MEANS 2 further comprises a finite impulse response (FIR) DIGITAL FILTER 2;

and wherein said FIR DIGITAL FILTER 2 performs the optimal tracking operation by matching the observed W-code spectrum and by optimizing the signal-to-noise (SNR) ratio of the cross-correlation process.

44. The system of claim 43, wherein said FIR DIGITAL FILTER 2 is implemented using a direct form transfer function.

45. The system of claim 43, wherein said FIR DIGITAL FILTER 2 is implemented using a cascade form transfer function.

46. The system of claim 43, wherein said FIR DIGITAL FILTER 2 is implemented using a parallel form transfer function.

47. The system of claim 11, wherein said DIGITAL FILTER MEANS 2 further comprises an infinite impulse response (IIR) DIGITAL FILTER 2;

and wherein said IIR DIGITAL FILTER 2 performs the optimal tracking operation by matching the observed W-code spectrum and by optimizing the signal-to-noise (SNR) ratio of the cross-correlation process.

48. The system of claim 47, wherein said IIR DIGITAL FILTER 2 is implemented using a direct form transfer function.

49. The system of claim 47, wherein said IIR DIGITAL FILTER 2 is implemented using a cascade form transfer function.

50. The system of claim 47, wherein said IIR DIGITAL FILTER 2 is implemented using a parallel form transfer function.

51. The system of claim 43, wherein said FIR DIGITAL FILTER 2 further comprises

a first L-bit SHIFT REGISTER MEANS (X1,X2, . . . Xm), m being an integer, for making an m-number of delayed copies of an input signal X, wherein a first copy of said input signal X1 is delayed by one sample clock SCLK, a second copy of said input signal X2 is delayed by two sample clocks, an (i) copy of said input signal Xi is delayed by (i) sample clocks, i being an integer, and an m-copy of said input signal Xm is delayed by (m) sample clocks;

an m-number of MULTIPLIER MEANS (C1, . . . Cm), wherein a first MULTIPLIER MEANS C1 transforms said X1 signal into a C1X1 signal; and

wherein a second MULTIPLIER MEANS C2 transforms said X2 signal into a C2X2 signal, and wherein an (i) MULTIPLIER MEANS Ci transform said Xi signal into a CiXi signal, and wherein an (m) MULTIPLIER MEANS transforms said Xm signal into a CmXm signal;

and an ADDER MEANS connected to each of said Ci MULTIPLIER MEANS for adding each said CiXi signals into an output function Your, wherein said output function Yout is equal to;

space="preserve" listing-type="equation">Yout=C1X1+C2X2+ . . . CmXm;

wherein said FIR DIGITAL FILTER MEANS 2 optimizes the signal-to-noise ratio by adapting to changes in the input signal X frequency spectrum.

52. The system of claim 47, wherein said IIR DIGITAL FILTER 2 further comprises

a first L-bit SHIFT REGISTER MEANS (X1,X2, . . . Xm), m being an integer, for making an m-number of delayed copies of an input signal X, wherein said input signal X comprises said I estimate of L2 W code, and wherein a first copy of said input signal X1 is delayed by one sample clock SCLK, a second copy of said input signal X2 is delayed by two sample clocks, an (i) copy of said input signal Xi is delayed by (i) sample clocks, i being an integer, and an m-copy of said input signal Xm is delayed by (m) sample clocks;

an m-number of MULTIPLIER MEANS (C1, . . . Cm), wherein a first MULTIPLIER MEANS C1 transforms said X1 signal into a C1X1 signal; and

wherein a second MULTIPLIER MEANS C2 transforms said X2 signal into a C2X2 signal, and wherein an (i) MULTIPLIER MEANS Ci transform said Xi signal into a CiXi signal, and wherein an (M) MULTIPLIER MEANS transforms said Xm signal into a CmXm signal;

a second L-bit SHIFT REGISTER MEANS (Y1,Y2, . . . Yn), n being an integer, for making an n-number of delayed copies of an output signal Y, and wherein a first copy of said output signal Y1 is delayed by one sample clock SCLK, a second copy of said output signal Y2 is delayed by two sample clocks, an (i) copy of said output signal Yi is delayed by (i) sample clocks, i being an integer, and an n-copy of said output signal Yn is delayed by (n) sample clocks;

an n-number of MULTIPLIER MEANS (B1, . . . Bn), wherein a first MULTIPLIER MEANS B1 transforms said Y1 signal into a B1 Y1 signal; and

wherein a second MULTIPLIER MEANS B2 transforms said Y2 signal into a B2Y2 signal, and wherein an (i) MULTIPLIER MEANS Bi transform said Yi signal into a BiYi signal, and wherein an (n) MULTIPLIER MEANS Bn transforms said Yn signal into a BnYn signal;

and an ADDER MEANS connected to each of said Ci and Bi MULTIPLIER MEANS for adding each said CiXi and BiYi signals into an output function Yout, wherein said output function Yout is equal to;

space="preserve" listing-type="equation">Yout=C1X1+C2X2+ . . . +CmXm+B1Y1+B2Y2+ . . . +BnYn;

and wherein said IIR DIGITAL FILTER MEANS 2 optimizes the signal-to-noise ratio by adapting to changes in the input signal X frequency spectrum.

53. A method for optimal correlation processing of L1 and L2 signals received from a SPS satellite by a correlation processing system;

said system comprising a RECEIVING MEANS and at least one DIGITAL CHANNEL PROCESSING MEANS;

said method comprising the steps of;

providing said RECEIVING MEANS and at least one said DIGITAL CHANNEL PROCESSING MEANS;

receiving a known C/A code modulated on L1 carrier frequency, an unknown Y code modulated on L1 carrier frequency signal, an unknown Y code modulated on L2 carrier frequency signal by said RECEIVING MEANS;

wherein said received L1, and L2 signals contain propagation noise; and

wherein said Y code comprises a known P code and an unknown W code;

generating local replica of said C/A code modulated on L1 carrier frequency signal by each said DIGITAL CHANNEL PROCESSING MEANS;

generating local replica of said P code modulated on L1 carrier frequency signal by each said DIGITAL CHANNEL PROCESSING MEANS;

wherein said locally generated replica of L1 signal does not contain propagation noise;

generating local replica of said P code modulated on L2 carrier frequency signal by each said DIGITAL CHANNEL PROCESSING MEANS;

wherein said locally generated replica of L2 signal does not contain propagation noise;

extracting of an estimate of said Y code from said L1 signal, and from said L2 signal by each said DIGITAL CHANNEL PROCESSING MEANS;

wherein said estimate signals contain propagation noise;

correlating a locally generated replica of C/A code with the received L1 code for obtaining an estimate of L1 group delay (L1 pseudo-range) and L1 carrier phase;

removing said P code from said locally extracted estimate of said L1 Y code by each said DIGITAL CHANNEL PROCESSOR to obtain a locally extracted estimate of said L1 W code;

removing said P code from said locally extracted estimate of said L2 Y code by each said DIGITAL CHANNEL PROCESSOR MEANS to obtain a locally extracted estimate of said L2 W code;

filtering estimate of said L1 W-code by a DIGITAL FILTER 1 with filter characteristics substantially similar to the W code frequency spectrum with no requirement for the filter characteristics to have any knowledge of the secret W code timing characteristics;

filtering estimate of said L2 W-code by a DIGITAL FILTER 2 with filter characteristics substantially similar to the W code frequency spectrum with no requirement for the filter characteristics to have any knowledge of the secret W code timing characteristics; and

multiplying said filtered estimates of L1 W-code with said filtered early, late, and punctual estimates of L2 W-code over a time period greater than a msec to ensure that the resulting correlated signal has a sufficient power for closing the L2-code and L2-carrier tracking loops.

54. The method of claim 53, said RECEIVING MEANS comprising a dual frequency patch ANTENNA MEANS, a FILTER/LNA MEANS, a DOWNCONVERTER MEANS, an IF PROCESSOR MEANS, a MASTER OSCILLATOR MEANS, and a FREQUENCY SYNTHESIZER MEANS;

wherein said step of receiving L1 and L2 satellite signals further comprises the steps of;

receiving said L1 and L2 satellite signals by said dual frequency patch ANTENNA MEANS;

performing filtering and low noise amplification of said L1 and L2 signals by said FILTER/LNA MEANS, wherein said FILTER/LNA MEANS determines the signal/noise ratio of the received signals L1 and L2;

mixing and converting said L1 and L2 signals by said DOWNCONVERTER MEANS;

transforming said converted L1 and L2 signals into digitally sampled quadrature versions of L1 and L2 signals (IL1, QL1, IL2, QL2) by said IF PROCESSOR MEANS; and

generating several timing signals by said FREQUENCY SYNTHESIZER MEANS.

55. The method of claim 54, said FILTER/LNA MEANS comprising a POWER SPLITTER MEANS, two separate BANDPASS FILTER MEANS, and a POWER COMBINER MEANS;

said step of performing filtering and low noise amplification of said L1 and L2 signals by said FILTER/LNA MEANS further comprises the steps of;

power splitting said single L1/L2 signal received by said ANTENNA MEANS into two separate L1 and L2 signals by said POWER SPLITTER MEANS;

filtering said L1 and L2 signals independently by said two separate BANDPASS FILTER MEANS;

combining said L1 and L2 signals into one combined signal L1/L2 before feeding said combined L1/L2 signal into said LNA by said POWER COMBINER MEANS.

56. The method of claim 54, said FREQUENCY SYNTHESIZER MEANS further comprising a PHASE DETECTOR MEANS, a LOOP FILTER MEANS, a VOLTAGE CONTROLLED OSCILLATOR (VCO) MEANS, a first DIVIDER MEANS, a second DIVIDER MEANS, and a third DIVIDER MEANS;

wherein said step of generating several timing signals by said FREQUENCY SYNTHESIZER MEANS further comprises the steps of;

comparing phases of two signals by said PHASE DETECTOR MEANS, first said signal being an output signal from said MASTER OSCILLATOR MEANS, second said signal being generated by said FREQUENCY SYNTHESIZER MEANS local reference signal, wherein minimum voltage output signal from said PHASE DETECTOR MEANS represents maximum phase alignment of said two signals;

filtering out high frequency voltage noise by said LOOP FILTER MEANS, wherein output LOOP FILTER MEANS voltage signal includes a low frequency voltage noise;

generating a 1st local oscillator (LO1) signal by said VCO, wherein voltage signal at the input of said VCO causes frequency change in said VCO output signal, and wherein said VCO nominal output signal is locked to said reference signal;

dividing said 1st LO1 signal by said first DIVIDER MEANS to obtain a 2nd local oscillator (LO2) signal;

dividing said 2nd LO2 signal by said second DIVIDER MEANS to obtain a sampling clock (SCLK); and

dividing said 2nd LO2 signal by said third DIVIDER MEANS to obtain a signal used for measurement of local reference time.

57. The method of claim 54, said FREQUENCY SYNTHESIZER MEANS further comprising a "Divide by 5" block, a PHASE DETECTOR MEANS, a LOOP FILTER MEANS, a VOLTAGE CONTROLLED OSCILLATOR (VCO) MEANS, a "Divide by 8" block, a "Divide by 7" block, and a "Divide by 25000" block;

wherein said step of generating several timing signals by said FREQUENCY SYNTHESIZER MEANS further comprises the steps of;

comparing 5 MHZ input signal from said MASTER OSCILLATOR MEANS with 5 MHZ signal from said "Divide by 5" block by said PHASE DETECTOR MEANS, wherein a minimum voltage output signal from said PHASE DETECTOR MEANS represents maximum phase alignment of two said 5 MHZ signals;

filtering out high frequency voltage noise by said LOOP FILTER MEANS;

generating a 1st local oscillator (LO1) signal by said VOLTAGE CONTROLLED OSCILLATOR (VCO) MEANS, wherein voltage signal at the input of said VCO causes frequency change in said VCO output signal, and wherein said VCO nominal output 1400 MHz signal is locked to said 5 MHz reference signal; and

wherein said 1400 MHz VCO output signal is used as said 1st local oscillator (LO1);

dividing said 1st LO1 1400 MHz signal by said "Divide by 8" block to obtain a 175 MHz signal, wherein said 175 MHz signal is used as a 2nd LO2 signal;

dividing said 2nd LO2 175 MHZ signal by said "Divide by 7" block to obtain a 25 MHZ signal, wherein said 25 MHz signal is used as a sampling clock (SCLK); and

dividing said 25 MHZ signal by said "Divide by 25000" block to obtain a 1 KHZ signal, wherein said 1 KHZ signal (MSEC) is used for measurement of local reference time.

58. The method of claim 54, said DOWNCONVERTER MEANS comprising a POWER SPLITTER MEANS, a first MULTIPLIER MEANS, a second MULTIPLIER MEANS, a first BANDPASS FILTER MEANS, a second BANDPASS FILTER MEANS, a first AMPLIFIER MEANS, and a second AMPLIFIER MEANS;

wherein said step of mixing and converting said L1 and L2 signals by said DOWNCONVERTER MEANS further comprises the steps of;

splitting said FILTER/LNA MEANS output L1/L2 signal into two signals L1 and L2 by said POWER SPLITTER MEANS;

producing a first mixed signal by multiplying said L1 signal with said 1st LO1 signal by said first MULTIPLIER MEANS;

producing a second mixed signal by multiplying said L2 signal with said 1st LO1 signal by said second MULTIPLIER MEANS;

filtering said first mixed signal by said first BANDPASS FILTER MEANS 1;

filtering said second mixed signal by said second BANDPASS FILTER MEANS 2;

amplifying said first filtered signal by said first AMPLIFIER MEANS 1; and

amplifying said second filtered signal by said second AMPLIFIER MEANS 2.

59. The method of claim 54, said IF PROCESSOR MEANS comprising a first POWER SPLITTER MEANS, a second POWER SPLITTER MEANS, a first MULTIPLIER MEANS, a second MULTIPLIER MEANS, a third MULTIPLIER MEANS, a fourth MULTIPLIER MEANS, a first AMPLIFIER MEANS, a second AMPLIFIER MEANS, a third AMPLIFIER MEANS, a fourth AMPLIFIER MEANS, a first one-bit A/D CONVERTER, a second one-bit A/D CONVERTER, a third one-bit A/D CONVERTER, a fourth one-bit A/D CONVERTER, a first FLIP-FLOP MEANS (FF1), a second FF2, a third FF3, and a fourth FF4;

wherein said step of transforming said converted L1 and L2 signals into digitally sampled quadrature versions of L1 and L2 signals (IL1, QL1, IL2, QL2) further comprises the steps of;

splitting said L1 signal into two signals by said first POWER SPLITTER MEANS;

splitting said L2 signal into two signals by said second POWER SPLITTER MEANS;

producing an IL1 signal by multiplying said L1 signal with an inphase (I) version of said 2nd LO2 signal by said first MULTIPLIER MEANS;

producing a QL1 signal by multiplying said L1 signal with a quadrature (Q) version of said 2nd LO2 signal by said second MULTIPLIER MEANS;

producing an IL2 signal by multiplying said L2 signal with an inphase (I) version of said 2nd LO2 signal by said third MULTIPLIER MEANS;

producing a QL2 signal by multiplying said L2 signal with a quadrature (Q) version of said 2nd LO2 signal by said fourth MULTIPLIER MEANS;

amplifying said IL1 signal by said first AMPLIFIER MEANS;

amplifying said QL1 signal by said second AMPLIFIER MEANS;

amplifying said IL2 signal by said third AMPLIFIER MEANS;

amplifying said QL2 signal by said fourth AMPLIFIER MEANS;

performing one-bit quantization operation on said IL1 signal by said first one-bit analog-to-digital (A/D) CONVERTER MEANS;

performing one-bit quantization operation on said QL1 signal by said second one-bit analog-to-digital (A/D) CONVERTER MEANS;

performing one-bit quantization operation on said IL2 signal by said third one-bit analog-to-digital (A/D) CONVERTER MEANS;

performing one-bit quantization operation on said QL2 signal by said fourth one-bit analog-to-digital (A/D) CONVERTER MEANS;

sampling said IL1 signal by clocking said IL1 signal through said FLIP-FLOP MEANS 1 (FF1) at sampling clock (SCLK) rate;

sampling said QL1 signal by clocking said QL1 signal through said FF2 at sampling clock (SCLK) rate;

sampling said IL2 signal by clocking said IL2 signal through said FF3 at sampling clock (SCLK) rate; and

sampling said QL2 signal by clocking said QL2 signal through said FF4 at sampling clock (SCLK) rate.

60. The method of claim 54, each said DIGITAL CHANNEL PROCESSING MEANS comprising a L1 TRACKER MEANS, a L2 TRACKER MEANS, and a MICROPROCESSOR MEANS system;

said method further comprising the steps of;

tracking L1 C/A code when encryption is ON and tracking L1 P code when encryption is OFF by said L1 TRACKER MEANS;

optimal encrypted L2 tracking when encryption is ON and tracking L2 P code when encryption is OFF by said L2 TRACKER MEANS; and

feeding said MICROPROCESSOR MEANS system by output signals from said L1 TRACKER MEANS and said L2 TRACKER MEANS.

61. The method of claim 60, said L1 TRACKER MEANS comprising a MULTIPLEXER MEANS 1, a carrier numerically controlled oscillator (CARRIER NCO MEANS 1), a CARRIER MIXER MEANS 1, a CODE GENERATOR MEANS 1, a CODE MIXER MEANS 1, a block CORRELATORS MEANS 1, a code numerically controlled oscillator (CODE NCO MEANS 1), a CODE MIXER MEANS 2, a DIGITAL FILTER 1 MEANS;

wherein said step of tracking L1 C/A code when Y code is ON and tracking L1 P code when Y code is OFF by said L1 TRACKER MEANS further comprises the steps of;

feeding said L1 TRACKER MEANS by digitized inphase IL1 and quadrature QL1 of L1 signal generated by said IF PROCESSOR MEANS;

synchronously clocking said L1 TRACKER MEANS by said SCLK signal outputted by said FREQUENCY SYNTHESIZER MEANS;

synchronously referencing said L1 TRACKER MEANS by said MSEC signal to local reference time, said MSEC signal being outputted by said FREQUENCY SYNTHESIZER MEANS;

feeding said L1 TRACKER MEANS by a CONTROL signal from said MICROPROCESSOR MEANS;

providing a locally generated replica of C/A code and locally generated replica of P code by said CODE GENERATOR 1 MEANS;

selecting a locally generated code C/A when Y code is ON and selecting a locally generated P code when Y code is OFF by said MULTIPLEXER MEANS 1;

generating inphase and quadrature components of digital carrier by said CARRIER NCO MEANS 1;

generating inphase IL1 and quadrature QL1 signals having zero carrier frequency by mixing digitized inphase IL1 and QL1 signals having carrier frequency with inphase and quadrature components of digital carrier by said CARRIER MIXER MEANS 1;

performing code correlation of said inphase IL1 and quadrature QL1 signals with said locally generated replica of C/A code or P-code by said CODE MIXER MEANS 1;

wherein when said L1 TRACKER MEANS carrier tracking loop is closed via said CARRIER NCO MEANS 1 the input to said CODE MIXER MEANS 1 represents the satellite signal L1 C/A code; and

wherein said CODE MIXER MEANS 1 performs said code correlation at 3 time points (early, punctual and late) on the autocorrelation function graph creating an early, a punctual and a late sample of the autocorrelation function;

integrating said early, punctual and late samples of said autocorrelation function over an integer multiple of EPOCH 1 signals by said block CORRELATORS MEANS 1;

feeding said MICROPROCESSOR MEANS system by an output signal of said CORRELATORS MEANS 1 at a rate of L1 C/A code EPOCH 1, wherein said MICROPROCESSOR MEANS uses said CORRELATORS MEANS 1 output signal to develop feedback signals for the L1 carrier tracking loop and for the L1 code tracking loop;

providing a clocking signal at a P code rate for driving said CODE GENERATOR 1 MEANS and providing a mechanism for aligning said locally generated replica of C/A code or a P-code with said incoming satellite signals C/A code or P-code by said code numerically controlled oscillator (CODE NCO 1 MEANS);

generating an estimate of L1 W code by removing said local replica of L1 P code from said estimate of L1 Y code by said CODE MIXER MEANS 2; and

processing said estimate of L1 W code by said DIGITAL FILTER 1 MEANS;

wherein said DIGITAL FILTER 1 MEANS outputs a W_L1.sbsb.--_F signal for further processing by said L2 TRACKER MEANS block, and wherein said DIGITAL FILTER 1 MEANS outputs a DCLK clocking signal for clocking said L2 TRACKER MEANS block.

62. The method of claim 61, wherein said DIGITAL FILTER MEANS 1 comprises a finite impulse response (FIR) DIGITAL FILTER 1;

and wherein said FIR DIGITAL FILTER 1 includes a first L-bit SHIFT REGISTER MEANS (X1,X2, . . . Xm);

X being an input signal;

m being an integer, an m-number of MULTIPLIER MEANS (C1, . . . Cm), and an ADDER MEANS connected to each of said Ci MULTIPLIER MEANS; and

wherein said step of reducing the bandwidth of said X input signal by said FIR DIGITAL FILTER MEANS 1 further comprises the steps of;

making an m-number of delayed copies of said input X signal by said first SHIFT REGISTER MEANS (X1,X2, . . . Xm), wherein a first copy X1 is delayed by one sample clock, a second copy X2 is delayed by two sample clocks, an (i) copy Xi is delayed by (i) sample clocks, i being an integer, and an m-copy Xm is delayed by (m) sample clocks;

transforming said first X1 signal into a C1X1-signal by said first MULTIPLIER MEANS C1;

transforming said second X2 signal into a C2X2 signal by said second MULTIPLIER MEANS C2;

performing the transformation of said Xi signal into a CiXi signal by said (i) MULTIPLIER MEANS Ci for each (i), wherein said (i) is an integer greater than 1 and less than m;

transforming said Xm signal into a CmXm signal by said (m) MULTIPLIER MEANS Cm;

adding each said CiXi signals into an output function Yout by said ADDER MEANS, wherein said output code function is equal to;

Yout=C1X1+C2X2+ . . . CmXm; and

optimizing the signal-to-noise ratio by adapting to changes in the input signal X frequency spectrum.

63. The method of claim 61, wherein said DIGITAL FILTER MEANS 1 comprises an infinite impulse response (IIR) DIGITAL FILTER 1;

and wherein said IIR DIGITAL FILTER 1 includes a first L-bit SHIFT REGISTER MEANS (X1,X2, . . . Xm);

X being an input signal;

m being an integer, an m-number of MULTIPLIER MEANS (C1, . . . Cm), a second L-bit SHIFT REGISTER MEANS (Y1,Y2, . . . Yn), n being an integer, an n-number of MULTIPLIER MEANS (B1, . . . Bn), and an ADDER MEANS connected to each of said Ci and Bi MULTIPLIER MEANS for adding each said CiXi and BiYi signals into an output function Yout, and wherein said step of reducing the bandwidth of said X input signal by said IIR DIGITAL FILTER MEANS 1 further comprises the steps of;

making an m-number of delayed copies of said input X signal by said first SHIFT REGISTER MEANS (X1,X2, . . . Xm), wherein a first copy X1 is delayed by one sample clock, a second copy X2 is delayed by two sample clocks, an (i) copy Xi is delayed by (i) sample clocks, i being an integer, and an m-copy Xm is delayed by (m) sample clocks;

transforming said first X1 signal into a C1X1-signal by said first MULTIPLIER MEANS C1;

transforming said second X2 signal into a C2X2 signal by said second MULTIPLIER MEANS C2;

performing the transformation of said Xi signal into a CiXi signal by said (i) MULTIPLIER MEANS Ci for each (i), wherein said (i) is an integer greater than 1 and less than k;

transforming said Xm signal into a CmXm signal by said (m) MULTIPLIER MEANS Cm;

making an n-number of delayed copies of said output Y signal by said second SHIFT REGISTER MEANS (Y1,Y2, . . . Yn), wherein a first copy Y1 is delayed by one sample clock, a second copy Y2 is delayed by two sample clocks, an (i) copy Yi is delayed by (i) sample clocks, i being an integer, and an n-copy Yn is delayed by (n) sample clocks;

transforming said first Y1 signal into a B1Y1-signal by said first MULTIPLIER MEANS B1;

transforming said second Y2 signal into a B2Y2 signal by said second MULTIPLIER MEANS B2;

performing the transformation of said Yi signal into a BiYi signal by said (i) MULTIPLIER MEANS Bi for each (i), wherein said (i) is an integer greater than 1 and less than n;

transforming said Yn signal into a BnYn signal by said (n) MULTIPLIER MEANS Bn;

adding each said CiXi and BiYi signals into an output function Yout by said ADDER MEANS, wherein said output code function is equal to;

Yout=C1X1+FC2X2+ . . . +CmXm+B1Y1+B2Y2+ . . . +BnYn; and

optimizing the signal-to-noise ratio by adapting to changes in the input signal X frequency spectrum.

64. The method of claim 60, said L2 TRACKER MEANS comprising a CARRIER NCO MEANS 2, a CODE NCO MEANS 2, a CODE GENERATOR 2 MEANS, a CARRIER MIXER MEANS 2, a CODE MIXER MEANS 3, a CODE MIXER MEANS 4, a MULTIPLEXER MEANS 2, a DIGITAL FILTER 2 MEANS, and a block CORRELATORS MEANS 2;

wherein said step of tracking an enhanced cross correlated W code when Y code is ON and tracking L2 P code when Y code is OFF by said L2 TRACKER MEANS further comprises the steps of;

feeding said L2 TRACKER MEANS by digitized inphase IL2 and quadrature QL2 of L2 signal outputted by said IF PROCESSOR MEANS;

synchronously clocking said L2 TRACKER MEANS by said SCLK signal outputted by said FREQUENCY SYNTHESIZER MEANS;

synchronously referencing said L2 TRACKER MEANS by said MSEC signal to local reference time, said MSEC signal being outputted by said FREQUENCY SYNTHESIZER MEANS;

feeding said L2 TRACKER MEANS by said W_L1.sbsb.--_F signal generated by said L1 TRACKER MEANS;

feeding said L2 TRACKER MEANS by said CONTROL signal from said MICROPROCESSOR MEANS;

clocking said DIGITAL FILTER 2 and said CORRELATORS 2 by said DCLK clock signal generated by said L1 TRACKER MEANS;

generating IL2 and QL2 signals having carrier frequency by said CARRIER NCO MEANS 2;

generating by said CARRIER MIXER MEANS 2 inphase IL2 and quadrature QL2 signals having zero carrier frequency by mixing said digitized inphase IL2 and quadrature QL2 signals having carrier frequency with said inphase and quadrature components IL2 and QL2 of digital carrier generated by said CARRIER NCO 2, wherein when said L2 TRACKER is locked onto said L2 signal, said I output of said CARRIER MIXER 2 MEANS represents an estimate of L2 Y code, and said Q output of said CARRIER MIXER 2 MEANS L2 contains no signal power;

producing a locally generated P code which is aligned with the incoming L2 satellite signal by said CODE GENERATOR 2 MEANS, wherein said CODE NCO 2 drives said CODE GENERATOR 2;

performing by said CODE MIXER MEANS 3 code correlation of said IL2 and QL2 having zero frequency signals outputted by said CARRIER MIXER 2 with said P code outputted by said CODE GENERATOR 2;

wherein said CODE MIXER 3 removes said P code from said L2 Y code; and

wherein said CODE MIXER 3 develops six outputs (I_E ;

I_P ;

I_L ;

Q_E ;

Q_P ;

Q_L) which are correlations of said I and Q signals outputted by said CARRIER MIXER MEANS 2 with said P code outputted by said CODE GENERATOR 2 at three time points (early, punctual, and late); and

wherein when the encryption is off said six outputs (I_E ;

I_P ;

I_L ;

Q_E ;

Q_P ;

Q_L) are used for closing said L2 code and carrier tracking loops;

filtering by said DIGITAL FILTER 2 MEANS said signals (I_E ;

I_P ;

I_L ;

Q_E ;

Q_P ;

Q_L) outputted by said CODE MIXER 3;

wherein said DIGITAL FILTER 2 MEANS outputs filtered signals (I_E.sbsb.--_F ;

I_P.sbsb.--_F ;

I_L.sbsb.--_F ;

Q_E.sbsb.--_F ;

Q_P.sbsb.--_F ;

Q_L.sbsb.--_F) at a rate determined by said clock signal DCLK at different time points (early, punctual, and late) on the autocorrelation function of said incoming P(Y) code and said local P code generated by said CODE GENERATOR 2;

performing code correlation by said CODE MIXER MEANS 4 of said (I_E.sbsb.--_F ;

I_P.sbsb.--_F ;

I_L.sbsb.--_F ;

Q_E.sbsb.--_F ;

Q_P.sbsb.--_F ;

Q_L.sbsb.--_F) signals outputted by said DIGITAL FILTER 2;

wherein said CODE MIXER MEANS 4 performs said code correlation at 3 time points (early, punctual and late) on the autocorrelation function graph creating an early, a punctual and a late sample of the autocorrelation function;

selecting under the control of MICROPROCESSOR MEANS by said MULTIPLEXER MEANS 2 the mode of operation when Y code is ON and OFF; and

wherein when Y code is OFF and satellite transmits the P code on L2 said MICROPROCESSOR MEANS selects the output of CODE MIXER MEANS 3; and

wherein when Y code is ON said MICROPROCESSOR MEANS selects the output of CODE MIXER MEANS 4;

integrating early, punctual and late samples of said autocorrelation function by said block CORRELATORS MEANS 2;

wherein said CORRELATORS MEANS 2 accumulates correlations at a rate of SCLK if the satellite is not encrypted and a rate of DCLK if the satellite is encrypted; and

feeding said MICROPROCESSOR MEANS by output signals of said CORRELATORS MEANS 2 at a rate of EPOCH 2;

wherein said MICROPROCESSOR MEANS uses said CORRELATORS MEANS 2 output signals to develop feedback signals for the L2 carrier tracking loop and for the L2 code tracking loop.

65. The method of claim 64, wherein said DIGITAL FILTER MEANS 2 comprises a finite impulse response (FIR) DIGITAL FILTER 2;

and wherein said FIR DIGITAL FILTER 2 includes a first L-bit SHIFT REGISTER MEANS (X1,X2, . . . Xm);

X being an input signal;

m being an integer, an m-number of MULTIPLIER MEANS (C1, . . . Cm), and an ADDER MEANS connected to each of said Ci MULTIPLIER MEANS; and

wherein said step of reducing the bandwidth of said X input signal by said FIR DIGITAL FILTER MEANS 2 further comprises the steps of;

making an m-number of delayed copies of said input X signal by said first SHIFT REGISTER MEANS (X1,X2, . . . Xm), wherein a first copy X1 is delayed by one sample clock, a second copy X2 is delayed by two sample clocks, an (i) copy Xi is delayed by (i) sample clocks, i being an integer, and an m-copy Xm is delayed by (m) sample clocks;

transforming said first X1 signal into a C1X1-signal by said first MULTIPLIER MEANS C1;

transforming said second X2 signal into a C2X2 signal by said second MULTIPLIER MEANS C2;

performing the transformation of said Xi signal into a CiXi signal by said (i) MULTIPLIER MEANS Ci for each (i), wherein said (i) is an integer greater than 1 and less than m;

transforming said Xm signal into a CmXm signal by said (m) MULTIPLIER MEANS Cm;

adding each said CiXi signals into an output function Yout by said ADDER MEANS, wherein said output code function is equal to;

Yout=C1X1+C2X2+ . . . CmXm; and

optimizing the signal-to-noise ratio by adapting to changes in the input signal X frequency spectrum.

66. The method of claim 64, wherein said DIGITAL FILTER MEANS 2 comprises an infinite impulse response (IIR) DIGITAL FILTER 2;

and wherein said IIR DIGITAL FILTER 2 includes a first L-bit SHIFT REGISTER MEANS (X1,X2, . . . Xm);

X being an input signal;

m being an integer, an m-number of MULTIPLIER MEANS (C1, . . . Cm), a second L-bit SHIFT REGISTER MEANS (Y1,Y2, . . . Yn), n being an integer, an n-number of MULTIPLIER MEANS (B1, . . . Bn), and an ADDER MEANS connected to each of said Ci and Bi MULTIPLIER MEANS for adding each said CiXi and BiYi signals into an output function Yout, and wherein said step of reducing the bandwidth of said X input signal by said IIR DIGITAL FILTER MEANS 2 further comprises the steps of;

making an m-number of delayed copies of said input X signal by said first SHIFT REGISTER MEANS (X1 ,X2, . . . Xm), wherein a first copy X1 is delayed by one sample clock, a second copy X2 is delayed by two sample clocks, an (i) copy Xi is delayed by (i) sample clocks, i being an integer, and an m-copy Xm is delayed by (m) sample clocks;

transforming said first X1 signal into a C1X1-signal by said first MULTIPLIER MEANS C1;

transforming said second X2 signal into a C2X2 signal by said second MULTIPLIER MEANS C2;

performing the transformation of said Xi signal into a CiXi signal by said (i) MULTIPLIER MEANS Ci for each (i), wherein said (i) is an integer greater than 1 and less than m;

transforming said Xm signal into a CmXm signal by said (m) MULTIPLIER MEANS Cm;

making an n-number of delayed copies of said output Y signal by said second SHIFT REGISTER MEANS (Y1,Y2, . . . Yn), wherein a first copy Y1 is delayed by one sample clock, a second copy Y2 is delayed by two sample clocks, an (i) copy Yi is delayed by (i) sample clocks, i being an integer, and an n-copy Yn is delayed by (n) sample clocks;

transforming said first Y1 signal into a B1Y1-signal by said first MULTIPLIER MEANS B1;

transforming said second Y2 signal into a B2Y2 signal by said second MULTIPLIER MEANS B2;

performing the transformation of said Yi signal into a BiYi signal by said (i) MULTIPLIER MEANS Bi for each (i), wherein said (i) is an integer greater than 1 and less than n;

transforming said Yn signal into a BnYn signal by said (n) MULTIPLIER MEANS Bn;

adding each said CiXi and BiYi signals into an output function Yout by said ADDER MEANS, wherein said output code function is equal to;

Yout=C1X1+C2X2+ . . . +CmXm+B1Y1+B2Y2+ . . . +BnYn;

and

optimizing the signal-to-noise ratio by adapting to changes in the input signal X frequency spectrum.

67. The method of claim 61, said CARRIER NCO MEANS 1 comprising an n-bit ACCUMULATOR MEANS, n being an integer, a first LATCH MEANS 1, a second LATCH MEANS 2, a first ADDER MEANS 1, a third LATCH MEANS 3, and a second LATCH MEANS 2, wherein said step of generating inphase and quadrature components of digital carrier by said CARRIER NCO MEANS 1 further comprises the steps of:

adding a new frequency word (B1 . . . Bn), B1 being the most significant bit (MSB), to a previous CARRIER NCO MEANS 1 output frequency word (Q1 . . . Qn) on each sample clock by said n-bit ACCUMULATOR MEANS;

wherein said ACCUMULATOR MEANS is caused to overflow periodically at the predetermined output frequency;

latching in said new frequency word (B1 . . . Bn) under the control signal of said MICROPROCESSOR MEANS by said first LATCH MEANS 1;

wherein L-top bits of said ACCUMULATOR MEANS output wave are used as an inphase version I of said CARRIER NCO MEANS 1 output wave;

L being an integer equal or greater to 1; and

wherein when the carrier tracking loop is locked L-top bits of said CARRIER NCO MEANS 1 output wave are used as the inphase version I of the carrier signal L1 which is phase locked with the satellite signal;

adding (01) binary code to the two top bits (S1 S2) of the CARRIER NCO MEANS 1 output (S1 . . . Sn) frequency word to obtain 2-top bits (R1 R2) by said first ADDER MEANS 1;

generating a quadrature version Q of carrier signal L1 by clocking in at the rate of the SCLK signal said 2-top bits (R1 R2) by said third LATCH MEANS;

wherein said LATCH MEANS 3 generates said QL1 signal in the from of L-bit word (R1 R2 S3 . . . SL); and

latching top m bits (C1 . . . Cm) of the CARRIER. NCO MEANS 1 output signal on the edge of the MSEC timing signal by said second LATCH MEANS 2;

m being an integer less than n;

wherein said (C1 . . . Cm) signal represents a carrier phase measurement signal.

68. The method of claim 67, said n-bit ACCUMULATOR MEANS comprising a second ADDER MEANS 2, and a fourth LATCH MEANS 4, wherein said step of adding a new frequency word (B1 . . . Bn), B1 being the most significant bit (MSB), to a previous CARRIER NCO 1 output frequency word (Q1 . . . Qn) on each sample clock by said n-bit ACCUMULATOR MEANS further comprises the steps of:

adding said frequency word (B1 . . . Bn) to a previous CARRIER NCO 1 frequency output (Q1 . . . Qn) on each sample clock by said second ADDER MEANS; and

generating said CARRIER NCO MEANS 1 output signal (Q1 . . . Qn) by said fourth LATCH MEANS 4;

wherein said fourth LATCH MEANS is caused to overflow at the desired output frequency; and

wherein L-top output bits of said fourth LATCH MEANS 4 are used as said CARRIER NCO MEANS 1 output signal.

69. The method of claim 64, said CARRIER NCO MEANS 2 comprising an n-bit ACCUMULATOR MEANS, n being an integer, a first LATCH MEANS 1, a second LATCH MEANS 2, a first ADDER MEANS 1, a third LATCH MEANS 3, and a second LATCH MEANS 2, wherein said step of generating inphase and quadrature components of digital carrier by said CARRIER NCO MEANS 1 further comprises the steps of:

adding a new frequency word (B1 . . . Bn), B1 being the most significant bit (MSB), to a previous CARRIER NCO MEANS 2 output frequency word (Q1 . . . Qn) on each sample clock by said n-bit ACCUMULATOR MEANS;

wherein said ACCUMULATOR MEANS is caused to overflow periodically at the predetermined output frequency;

latching in said new frequency word (B1 . . . Bn) under the control signal of said MICROPROCESSOR MEANS by said first LATCH MEANS 1;

wherein L-top bits of said ACCUMULATOR MEANS output wave are used as an inphase version I of said CARRIER NCO MEANS 2 output wave;

L being an integer equal or greater to 1; and

wherein when the carrier tracking loop is locked L-top bits of said CARRIER NCO MEANS 2 output wave are used as the inphase version I of the carrier signal L2 which is phase locked with the satellite signal;

adding (01) binary code to the two top bits (S1 S2) of the CARRIER NCO MEANS 2 output (S1 . . . Sn) frequency word to obtain 2-top bits (R1 R2) by said first ADDER MEANS 1;

generating a quadrature version Q of carrier signal L2 by clocking in at the rate of the SCLK signal said 2-top bits (R1 R2) by said third LATCH MEANS;

wherein said LATCH MEANS 3 generates said QL2 signal in the from of L-bit word (R1 R2 S3 . . . SL); and

latching top m bits (C1 . . . Cm) of the CARRIER NCO MEANS 2 output signal on the edge of the MSEC timing signal by said second LATCH MEANS 2;

m being an integer less than n;

wherein said (C1 . . . Cm) signal represents a carrier phase measurement signal.

70. The method of claim 69, said n-bit ACCUMULATOR MEANS comprising a second ADDER MEANS 2, and a fourth LATCH MEANS 4, wherein said step of adding a new frequency word (B1 . . . Bn), B1 being the most significant bit (MSB), to a previous CARRIER NCO MEANS 2 output frequency word (Q1 . . . Qn) on each sample clock by said n-bit ACCUMULATOR MEANS further comprises the steps of:

adding said frequency word (B1 . . . Bn) to a previous CARRIER NCO MEANS 2 frequency output (Q1 . . . Qn) on each sample clock by said second ADDER MEANS; and

generating said CARRIER NCO MEANS 2 output signal (Q1 . . . Qn) by said fourth LATCH MEANS;

wherein said fourth LATCH MEANS is caused to overflow at the desired output frequency; and

wherein L-top output bits of said fourth LATCH MEANS 4 are used as said CARRIER NCO MEANS 2 output signal.

71. The method of claim 61, said CARRIER MIXER MEANS 1 comprising a first MULTIPLIER MEANS 1, a second MULTIPLIER MEANS 2, a first ADDER MEANS 1, a third MULTIPLIER MEANS 3, a fourth MULTIPLIER MEANS 4 and a second ADDER MEANS 2, wherein said step of generating inphase IL1 and quadrature QL1 signals having zero carrier frequency by mixing digitized inphase IL1 and QL1 signals having carrier frequency with inphase and quadrature components of digital carrier by said CARRIER MIXER MEANS 1 further comprises the steps of:

generating a (IL1)*I signal by performing a multiplication operation of an inphase version I of L1 satellite carrier signal and an inphase version I of carrier frequency by said first MULTIPLIER MEANS 1;

generating a (QL1)*Q signal by performing a multiplication operation of a quadrature version Q of L1 satellite carrier signal and a quadrature version Q of carrier frequency by said second MULTIPLIER MEANS 2,

subtracting said (QL1)*Q signal from said (IL1)*I signal by said first ADDER MEANS 1;

generating a (IL1)*Q signal by performing a multiplication operation of an inphase version I of L1 satellite carrier signal and a quadrature version Q of carrier frequency by said third MULTIPLIER MEANS 3;

generating a (QL1)*I signal by performing a multiplication operation of a quadrature version Q of L1 satellite carrier signal and an inphase version I of carrier frequency by said fourth MULTIPLIER MEANS 4; and

adding said (QL1)*I signal to said (IL1)*Q signal by said second ADDER MEANS 2.

72. The method of claim 64, said CARRIER MIXER MEANS 2 comprising a first MULTIPLIER MEANS 1, a second MULTIPLIER MEANS 2, a first ADDER MEANS 1, a third MULTIPLIER MEANS 3, a fourth MULTIPLIER MEANS 4 and a second ADDER MEANS 2, wherein said step of generating inphase IL2 and quadrature QL2 signals having zero carrier frequency by mixing digitized inphase IL2 and QL2 signals having carrier frequency with inphase and quadrature components of digital carrier by said CARRIER MIXER MEANS 2 further comprises the steps of:

generating a (IL2)*I signal by performing a multiplication operation of an inphase version I of L2 satellite carrier signal and an inphase version I of carrier frequency by said first MULTIPLIER MEANS 1;

generating a (QL2)*Q signal by performing a multiplication operation of a quadrature version Q of L2 satellite carrier signal and a quadrature version Q of carrier frequency by said second MULTIPLIER MEANS 2,

subtracting said (QL2)*Q signal from said (IL2)*I signal by said first ADDER MEANS 1;

generating a (IL2)*Q signal by performing a multiplication operation of an inphase version I of L2 satellite carrier signal and a quadrature version Q of carrier frequency by said third MULTIPLIER MEANS 3;

generating a (QL2)*I signal by performing a multiplication operation of a quadrature version Q of L2 satellite carrier signal and an inphase version I of carrier frequency by said fourth MULTIPLIER MEANS 4; and

adding said (QL2)*I signal to said (IL2)*Q signal by said second ADDER MEANS 2.

73. The method of claim 61, said CODE MIXER MEANS 1 comprising a first MULTIPLIER MEANS 1, a second MULTIPLIER MEANS 2, a third MULTIPLIER MEANS 3, a fourth MULTIPLIER MEANS, a fifth MULTIPLIER MEANS, and a sixth MULTIPLIER MEANS;

wherein the step of performing code correlation of said inphase IL1 and quadrature QL1 signals with said locally generated replica of C/A code by said CODE MIXER MEANS 1 at 3 time points (early, punctual and late) on the autocorrelation function graph creating an early, a punctual and a late sample of the autocorrelation function, further comprises the steps of;

multiplying said incoming I signal with an early version (E) of said local C/A code or P-code by said first MULTIPLIER MEANS;

multiplying said incoming I signal with a punctual version (P) of said local C/A code or P-code by said second MULTIPLIER MEANS;

multiplying said incoming I signal with a late version (L) of said local C/A code or P-code by said third MULTIPLIER MEANS;

multiplying said incoming Q signal with an early version (E) of said local C/A code or P-code by said fourth MULTIPLIER MEANS;

multiplying said incoming Q signal with a punctual version (P) of said local C/A code or P-code by said fifth MULTIPLIER MEANS; and

multiplying said incoming Q signal with a late version (L) of said local C/A code or P-code by said sixth MULTIPLIER MEANS.

74. The method of claim 61, said CODE MIXER MEANS 2 comprising a MULTIPLIER MEANS, said step of generating an estimate of L1 W code by removing said local replica of L1 P code from said estimate of L1 Y code by said CODE MIXER MEANS 2 further comprises the step of:

generating a L1 W code estimate by multiplying said incoming L1 Y code estimate with said locally generated L1 P code by said MULTIPLIER MEANS.

75. The method of claim 64, wherein said step of producing by said CODE GENERATOR 2 MEANS a locally generated P code which is aligned with the incoming L2 satellite signal further includes a step of driving said CODE GENERATOR 2 by said CODE NCO 2.

76. The method of claim 64, said CODE MIXER MEANS 3 comprising a first MULTIPLIER MEANS, a second MULTIPLIER MEANS, a third MULTIPLIER MEANS, a fourth MULTIPLIER MEANS, a fifth MULTIPLIER MEANS, and a sixth MULTIPLIER MEANS, wherein said step of performing by said CODE MIXER MEANS 3 code correlation of said IL2 and QL2 having zero frequency signals outputted by said CARRIER MIXER 2 with said P code outputted by said CODE GENERATOR 2 further includes the steps of:

generating by said first MULTIPLIER MEANS an early I_E correlation of L2 W code by multiplying said incoming I estimate of L2 Y code at early point (E) on the autocorrelation function graph with said locally generated L2 P code;

generating by said second MULTIPLIER MEANS a punctual I_P correlation of L2 W code by multiplying said incoming I estimate of L2 Y code at punctual point (P) on the autocorrelation function graph with said locally generated L2 P code;

generating by said third MULTIPLIER MEANS a late I_L correlation of L2 W code by multiplying said incoming I estimate of L2 Y code at late point (L) on the autocorrelation function graph with said locally generated L2 P code;

generating by said fourth MULTIPLIER MEANS an early Q_E correlation of L2 W code by multiplying said incoming Q estimate of L2 Y code at early point (E) on the autocorrelation function graph with said locally generated L2 P code;

generating by said fifth MULTIPLIER MEANS a punctual Q_P correlation of L2 W code by multiplying said incoming Q estimate of L2 Y code at punctual point (P) on the autocorrelation function graph with said locally generated L2 P code; and

generating by said sixth MULTIPLIER MEANS a late Q_L correlation of L2 W code by multiplying said incoming Q estimate of L2 Y code at late point (L) on the autocorrelation function graph with said locally generated L2 P code.

77. The method of claim 64, said CODE MIXER MEANS 4 comprising a first MULTIPLIER MEANS, a second MULTIPLIER MEANS, a third MULTIPLIER MEANS, a fourth MULTIPLIER MEANS, a fifth MULTIPLIER MEANS, and a sixth MULTIPLIER MEANS;

wherein said step of performing correlation by said CODE MIXER MEANS 4 at 3 time points (early, punctual and late) on the autocorrelation function graph further comprises the steps of;

multiplying by said first MULTIPLIER MEANS said I_E.sbsb.--_F signal with said W_L1.sbsb.--_F signal;

wherein said first MULTIPLIER outputs an E-early with respect to the P-code autocorrelation function correlations E_EW.sbsb.--_F of the IL2 signal;

multiplying by said second MULTIPLIER MEANS said I_P.sbsb.--_F signal with said W_L1.sbsb.--_F signal;

wherein said second MULTIPLIER outputs a P-punctual with respect to the P-code autocorrelation function correlations I_PW.sbsb.--_F of the IL2 signal;

multiplying by said third MULTIPLIER MEANS said I_L.sbsb.--_F signal with said W_L1.sbsb.--_F signal;

wherein said third MULTIPLIER outputs an L-late with respect to the P-code autocorrelation function correlations I_LW.sbsb.--_F of the IL2 signal;

multiplying by said fourth MULTIPLIER MEANS said Q_E.sbsb.--_F signal with said W_L1.sbsb.--_F signal;

wherein said fourth MULTIPLIER outputs an E-early with respect to the P-code autocorrelation function correlations Q_EW.sbsb.--_F of the IL2 signal;

multiplying by said fifth MULTIPLIER MEANS said Q_P.sbsb.--_F signal with said W_L1.sbsb.--_F signal;

wherein said fifth MULTIPLIER outputs a P-punctual with respect to the P-code autocorrelation function correlations Q_PW.sbsb.--_F of the IL2 signal; and

multiplying by said sixth MULTIPLIER MEANS said Q_L.sbsb.--_F signal with said W_L1.sbsb.--_F signal;

wherein said sixth MULTIPLIER outputs an L-late with respect to the P-code autocorrelation function correlations Q_LW.sbsb.--_F of the IL2 signal.

78. The method of claim 61, said CODE GENERATOR 1 MEANS comprising a first DIVIDING MEANS, a C/A CODE GENERATOR MEANS, and a P CODE GENERATOR MEANS, wherein said step of providing a locally generated replica of C/A code and locally generated replica of P code by said CODE GENERATOR 1 MEANS further comprises the steps of:

providing a C/A CODE GENERATOR MEANS clock signal by dividing an input signal from said CODE NCO 1 MEANS by said first DIVIDING MEANS;

generating by said C/A CODE GENERATOR said C/A code signal and said EPOCH 1 signal under the CONTROL signal of said MICROPROCESSOR MEANS, wherein said C/A code signal is the locally generated C/A code, and wherein said EPOCH 1 signal is the repetition rate of said C/A code, and wherein said C/A CODE GENERATOR can be adjusted under said CONTROL signal to generate a particular satellite'"'"'s C/A code; and

generating by said P CODE GENERATOR MEANS said P-code signal, wherein said P CODE GENERATOR MEANS is clocked by said CODE NCO 1 MEANS signal under the CONTROL signal of said MICROPROCESSOR MEANS, and wherein said P CODE GENERATOR can be adjusted under said CONTROL signal to generate a particular satellite'"'"'s P code.

79. The method of claim 64, said CODE GENERATOR 2 MEANS comprising a first DIVIDING MEANS, a C/A CODE GENERATOR MEANS, and a P CODE GENERATOR MEANS, wherein said step of providing a locally generated replica of C/A code and locally generated replica of P code by said CODE GENERATOR 1 MEANS further comprises the steps of:

providing a C/A CODE GENERATOR MEANS clock signal by dividing an input signal from said CODE NCO 2 MEANS by said first DIVIDING MEANS;

generating by said C/A CODE GENERATOR said EPOCH 2 signal under the CONTROL signal of said MICROPROCESSOR MEANS; and

generating by said P CODE GENERATOR MEANS said P-code signal, wherein said P CODE GENERATOR MEANS is clocked by said CODE NCO 2 MEANS signal under the CONTROL signal of said MICROPROCESSOR MEANS, and wherein said P CODE GENERATOR can be adjusted under said CONTROL signal to generate a particular satellite'"'"'s P code.

80. The method of claim 61, said block CORRELATORS MEANS 1 comprising a first UP/DOWN COUNTER MEANS 1, a first LATCH MEANS, a second UP/DOWN COUNTER MEANS 2, a second LATCH MEANS, a third UP/DOWN COUNTER MEANS 3, a third LATCH MEANS, a fourth UP/DOWN COUNTER MEANS 4, a fourth LATCH MEANS, a fifth UP/DOWN COUNTER MEANS 5, a fifth LATCH MEANS, a sixth UP/DOWN COUNTER MEANS 6, and a sixth LATCH MEANS;

wherein said step of integrating said early, punctual and late samples of said autocorrelation function by said block CORRELATORS MEANS 1 further comprises the steps of;

integrating said IE signal across a period defined by said C/A EPOCH 1 signal by said first UP/DOWN COUNTER MEANS 1;

wherein said UP/DOWN COUNTER MEANS 1 adds if the input is positive and subtracts if it is negative and is reset on EPOCH 1;

using said first LATCH MEANS for reading said integrated IE signal by said MICROPROCESSOR MEANS system;

integrating said IP across a period defined by said C/A EPOCH 1 signal by said second UP/DOWN COUNTER MEANS 2;

using said second LATCH MEANS for reading said integrated IP signal by said MICROPROCESSOR MEANS system;

integrating said IL across a period defined by said C/A EPOCH 1 signal by said third UP/DOWN COUNTER MEANS;

using said third LATCH MEANS for reading said integrated IL signal by said MICROPROCESSOR MEANS system;

integrating said QE across a period defined by said C/A EPOCH 1 signal by said fourth UP/DOWN COUNTER MEANS 4;

using said fourth LATCH MEANS for reading said integrated QE signal by said MICROPROCESSOR MEANS system;

integrating said QP across a period defined by said C/A EPOCH 1 signal by said fifth UP/DOWN COUNTER MEANS 5;

using said fifth LATCH MEANS for reading said integrated QP signal by said MICROPROCESSOR MEANS system;

integrating said QL across a period defined by said C/A EPOCH 1 signal by said sixth UP/DOWN COUNTER MEANS 6; and

using said sixth LATCH MEANS for reading said integrated QP signal by said MICROPROCESSOR MEANS system;

wherein said block CORRELATORS MEANS 1 is used for integrating said IE (inphase early), said IP (inphase punctual), said IL (inphase late), said QE (quadrature early), said QP (quadrature punctual), and said QL (quadrature late) versions of the correlated samples of said L1 C/A code with said locally generated version of C/A code across a time period given by a multiple of L1 C/A EPOCH 1 code; and

wherein said IE, IL, QE, and QL are used by said code tracking loop by forming;

a code phase estimate=KI(IE-IL), when said carrier loop is locked;

or

a code phase estimate=KI[(IE² +QE²)^1/2 -(IL² +QL²)^1/2 ], when said carrier loop is not locked;

K1 being an L1 code loop gain factor; and

wherein said IP, and QP are used by said carrier tracking loop by forming;

a carrier phase estimate=arctan(QP/IP).

81. The method of claim 64, said block CORRELATORS MEANS 2 comprising a first UP/DOWN COUNTER MEANS 1, a first LATCH MEANS, a second UP/DOWN COUNTER MEANS 2, a second LATCH MEANS, a third UP/DOWN COUNTER MEANS 3, a third LATCH MEANS, a fourth up/down COUNTER MEANS 4, a fourth LATCH MEANS, a fifth UP/DOWN COUNTER MEANS 5, a fifth LATCH MEANS, a sixth UP/DOWN COUNTER MEANS 6, and a sixth LATCH MEANS;

wherein said step of integrating said early, punctual and late samples of said autocorrelation function by said block CORRELATORS MEANS 2 further comprises the steps of;

integrating said IE across a period defined by said EPOCH 2 signal by said first UP/DOWN COUNTER MEANS 1;

wherein said UP/DOWN COUNTER MEANS adds if the input is positive and subtracts if it is negative and is reset on EPOCH 2 signal;

using said first LATCH MEANS for reading said integrated IE signal by said MICROPROCESSOR MEANS system;

integrating said IP across a period defined by said EPOCH 2 signal by said second UP/DOWN COUNTER MEANS 2;

using said second LATCH MEANS for reading said integrated IP signal by said MICROPROCESSOR MEANS system;

integrating said IL across a period defined by said EPOCH 2 signal by said third UP/DOWN COUNTER MEANS 3;

using said third LATCH MEANS for reading said integrated IL signal by said MICROPROCESSOR MEANS system;

integrating said QE across a period defined by said EPOCH 2 signal by said fourth UP/DOWN COUNTER MEANS 4;

using said fourth LATCH MEANS for reading said integrated QE signal by said MICROPROCESSOR MEANS system;

integrating said QP across a period defined by said EPOCH 2 signal by said fifth UP/DOWN COUNTER MEANS 5;

using said fifth LATCH MEANS for reading said integrated QP signal by said MICROPROCESSOR MEANS system;

integrating said QL across a period defined by said EPOCH 2 signal by said sixth UP/DOWN COUNTER MEANS; and

using said sixth LATCH MEANS for reading said integrated QL signal by said MICROPROCESSOR MEANS system;

wherein said block CORRELATORS MEANS 2 is used for integrating said IE (inphase early), said IP (inphase punctual), said IL (inphase late), said QE (quadrature early), said QP (quadrature punctual), and said QL (quadrature late) version of the correlated samples between filtered estimates of L1 and L2 W codes across a time period given by a multiple of EPOCH 2 signal; and

wherein said IE, IL, QE, and QL are used by said code tracking loop by forming;

a code phase estimate=K2(IE-IL), when said carrier loop is locked;

or

a code phase estimate=K2[(IE² +QE²)^1/2 -(IL² +QL²)^1/2], when said carrier loop is not locked;

K2 being an L2 code loop gain factor; and

wherein said IP, and QP signals are used by said carrier tracking loop by forming;

a carrier phase estimate=arctan(QP/IP).

82. The method of claim 61, said CODE NCO 1 MEANS comprising a n-bit ADDER MEANS, a n-bit LATCH MEANS, n being an integer, and a MULTIPLEXER MEANS;

wherein said step of providing a clocking signal at C/A code rate and a clocking signal at P code rate for said CODE GENERATOR 1 MEANS by said CODE NCO 1 MEANS further comprises the steps of;

adding on each sample clock edge the output of said LATCH MEANS to the output of said MULTIPLEXER MEANS by said ADDER MEANS;

generating one of three n-bit values (N, M or SHIFT) by said MULTIPLEXER MEANS;

outputting under normal operation CODE NCO 1 MEANS frequency=(N×

SCLK)/(2ⁿ -M+N) by said CODE NCO 1 MEANS; and

outputting under code phase shift operation code phase shift=(M-SHIFT)/(2ⁿ -M+N) by said CODE NCO 1 MEANS.

83. The method of claim 82, said CODE NCO 1 MEANS comprising a 12-bit ADDER MEANS, a 12-bit LATCH MEANS, and a MULTIPLEXER MEANS;

wherein said step of providing a clocking signal at C/A code rate and a clocking signal at P code rate for said CODE GENERATOR 1 MEANS by said CODE NCO 1 MEANS further comprises the steps of;

adding on each sample clock edge the output of said LATCH MEANS to the output of said MULTIPLEXER MEANS by said ADDER MEANS;

generating one of three 12-bit values (N, M or SHIFT) by said MULTIPLEXER MEANS;

outputting under normal operation CODE NCO 1 MEANS frequency=10.23 MHz by said CODE NCO 1 MEANS; and

outputting under code phase shift operation code phase shift=(2619-SHIFT)/2500 sample clocks by said CODE NCO 1 MEANS.

84. The method of claim 64, said CODE NCO 2 MEANS comprising a n-bit ADDER MEANS, a n-bit LATCH MEANS, n being an integer, and a MULTIPLEXER MEANS;

wherein said step of providing a clocking signal for said CODE GENERATOR 2 MEANS by said CODE NCO 2 MEANS further comprises the steps of;

adding on each sample clock edge the output of said LATCH MEANS to the output of said MULTIPLEXER MEANS by said ADDER MEANS;

generating one of three n-bit values (N, M or SHIFT) by said MULTIPLEXER MEANS;

outputting under normal operation CODE NCO 2 MEANS frequency=(N×

SCLK)/(2ⁿ -M+N) by said CODE NCO 2 MEANS; and

outputting under code phase shift operation code phase shift=(M-SHIFT)/(2ⁿ -M+N) by said CODE NCO 2 MEANS.

85. The method of claim 84, said CODE NCO 2 MEANS comprising a 12-bit ADDER MEANS, a 12-bit LATCH MEANS, and a MULTIPLEXER MEANS;

wherein said step of providing a clocking signal for said CODE GENERATOR 2 MEANS by said CODE NCO 2 MEANS further comprises the steps of;

adding on each sample clock edge the output of said LATCH MEANS to the output of said MULTIPLEXER MEANS by said ADDER MEANS;

generating one of three 12-bit values (N, M or SHIFT) by said MULTIPLEXER MEANS;

outputting under normal operation CODE NCO 2 MEANS frequency=10.23 MHz by said CODE NCO 2 MEANS; and

outputting under code phase shift operation code phase shift=(2619-SHIFT)/2500 sample clocks by said CODE NCO 2 MEANS.

86. A method of acquisition of an L1 and an L2 satellite signals by a SPS RECEIVER;

said SPS RECEIVER comprising a L1 TRACKER MEANS, a L2 TRACKER MEANS, and a MICROPROCESSOR SYSTEM;

said L1 TRACKER MEANS comprising a MULTIPLEXER MEANS 1, a CARRIER NCO MEANS 1, a CARRIER MIXER MEANS 1, a CODE GENERATOR 1 MEANS, a CODE MIXER MEANS 1, a CODE NCO MEANS 1, a CODE MIXER MEANS 2, a DIGITAL FILTER 1, and a CORRELATORS 1;

said L2 TRACKER comprising a CODE GENERATOR MEANS 2, a CARRIER NCO MEANS 2, a CARRIER MIXER MEANS 2, a CODE NCO MEANS 2, a CODE MIXER MEANS 3, a CODE MIXER MEANS 4, a DIGITAL FILTER 2, a MULTIPLEXER 2, and a block CORRELATORS MEANS 2;

wherein said method further comprises the steps of;

locking L1 C/A code tracking loop by said MICROPROCESSOR SYSTEM;

locking L1 C/A carrier tracking loop by said MICROPROCESSOR SYSTEM;

computing the L2 carrier frequency aiding term by said MICROPROCESSOR SYSTEM using the value of L1 frequency;

applying said L2 frequency aiding term to said CARRIER NCO MEANS 2;

wherein said L1 and L2 satellite signals are separated in time by ionospheric delay;

setting up a P CODE GENERATOR in said CODE GENERATOR 1 and in said CODE GENERATOR 2;

adjusting said CODE NCO 2 phase to compensate for the ionospheric delay between said L1 and said L2 signals until power is found in said L2 CORRELATORS MEANS 2;

locking the L2 carrier tracking loop using said MICROPROCESSOR SYSTEM; and

locking the L2 code tracking loop using said MICROPROCESSOR SYSTEM.

87. The method of claim 86, wherein said method further comprises the steps of:

reading said L1 CORRELATORS MEANS and said L2 CORRELATORS MEANS by said MICROPROCESSOR MEANS;

forming the L1 code tracking loop and applying the output to said CODE NCO 1 MEANS;

forming the L1 carrier tracking loop and applying the output to said CARRIER NCO MEANS 1;

computing the L2 frequency aiding term;

forming the L2 code tracking loop and applying the output to said CODE NCO MEANS 2;

forming the L2 carrier tracking loop and applying the output to said CARRIER NCO MEANS 2;

performing the L1 and L2 carrier phase measurements by reading CARRIER NCO MEANS 1'"'"'s output phase and CARRIER NCO MEANS 2'"'"'s output phase at a chosen MSEC reference time; and

performing the L1 and L2 code phase measurements by keeping track in said MICROPROCESSOR MEANS of what shifts have been applied to said CODE NCO MEANS 1 and CODE NCO MEANS 2 respectively;

whereby the tracking of said satellite signals L1 and a L2 is achieved.

88. A method of optimal acquisition of an L1 and an L2 satellite signals by an ADJUSTABLE OPTIMAL SATELLITE RECEIVER;

said ADJUSTABLE OPTIMAL SATELLITE RECEIVER comprising a plurality of ADJUSTABLE DIGITAL CHANNEL PROCESSORS;

said method comprising the steps of;

providing said ADJUSTABLE OPTIMAL SATELLITE RECEIVER;

observing a plurality of the SPS satellites;

discovering a W code frequency spectrum for each said SPS satellite; and

adjusting each said ADJUSTABLE DIGITAL CHANNEL PROCESSORS to the observed W code frequency spectrum of one said SPS satellite;

wherein said ADJUSTABLE OPTIMAL SATELLITE RECEIVER operates optimally for all satellites tracked with adjustment on the per satellite basis.