Bus architecture for digital signal processor allowing time multiplexed access to memory banks

• US 5,611,075 A
• Filed: 07/29/1996
• Issued: 03/11/1997
• Est. Priority Date: 10/04/1994
• Status: Expired due to Term

• Current Assignee: Analog Devices, Inc.
• Original Assignee: Analog Devices, Inc.
• Inventors: Garde, Douglas
• Primary Examiner(s): Coleman, Eric
• Application Number:
  US08/681,905
• Time in Patent Office: 225 Days
• Field of Search: 395/480, 395/800
• US Class Current: 711/153
• CPC Class Codes: G06F 13/1647 with interleaved bank access
• CPC Class Codes: G06F 15/7846 On-chip cache and off-chip main memory

Abstract

A monolithic digital signal processor includes a core processor for performing digital signal computations, an I/O processor for controlling external access to and from the digital signal processor through an external port, first and second memory banks for storing instructions and data for the digital signal computations, and first and second buses interconnecting the core processor, the I/O processor and the memory banks. The core processor and the I/O processor access the memory banks on the first bus without interference on different clock phases of a clock cycle. The internal memory and the I/O processor of the digital signal processor are assigned to a region of a global memory space, which facilitates multiprocessing configurations. In a multiprocessor system, each digital signal processor is assigned a processor ID. The digital signal processor includes a bus arbitration circuit for controlling access to an external bus through the external port. The digital signal processor may include one or more serial ports and one or more link ports for point-to-point communication with external devices. A DMA controller controls DMA transfers through the external port, the serial ports and the link ports.

Claims

1. A digital signal processor, comprising:

a core processor for performing digital signal computations;

an I/O processor for controlling external access to and from the digital signal processor;

first and second pipeline memory banks for storing instructions and data for the digital signal computations;

a first bus and a second bus interconnecting said core processor and said first and second pipeline memory banks, said first bus interconnecting said I/O processor and said first and second pipeline memory banks;

an external port bus interconnecting said core processor and said I/O processor;

an external port circuit for interconnecting said external port bus to an external bus, said external bus providing interconnection to an external device, whereby said I/O processor communicates with said external device on said external port bus without interfering with access by said core processor to said first and second pipeline memory banks on said first bus and said second bus;

a clock circuit for generating a first clock phase and a second clock phase in response to a clock signal; and

means for coupling said core processor to one of said pipeline memory banks on said first bus during said second clock phase and for coupling said I/O processor to one of said pipeline memory banks on said first bus during said first clock phase, whereby said core processor and said I/O processor access said first and second pipeline memory banks on said first bus during different clock phases of a clock cycle.

2. A digital signal processor as defined in claim 1 wherein said I/O processor includes means for coupling data between said external port bus and said pipeline memory banks on said first bus during said first clock phase, whereby said external device accesses said pipeline memory banks without interfering with operation of said core processor.

3. A digital signal processor as defined in claim 1 wherein said I/O processor includes at least one data communication port and means for coupling data between said data communication port and said pipeline memory banks on said first bus during said first clock phase, whereby said data communication port accesses said pipeline memory banks without interfering with operation of said core processor.

4. A method for digital signal processing with a digital signal processor comprising a core processor for performing digital signal computations, an I/O processor for controlling external access to and from the digital signal processor and first and second pipeline memory banks for storing instructions and data for the digital signal computations, said method comprising the steps of:

interconnecting said core processor and said first and second pipeline memory banks on a first bus and a second bus, and interconnecting said I/O processor and said first and second pipeline memory banks on said first bus;

generating a first clock phase and a second clock phase in response to a clock signal;

coupling said core processor to one of said pipeline memory banks on said first bus during said second clock phase and coupling said I/O processor to one of said pipeline memory banks on said first bus during said first clock phase, whereby said core processor and said I/O processor access said first and said second pipeline memory banks on said first bus during different clock phases of a clock cycle;

interconnecting said I/O processor to an external device on an external port bus; and

coupling data between said external port bus and said pipeline memory banks on said first bus during said first clock phase, whereby said external device accesses said pipeline memory banks without interfering with operation of said core processor.

5. A method as defined in claim 4 further including the step of coupling data between a data communication port and said pipeline memory banks on said first bus during said first clock phase, whereby said data communication port accesses said pipeline memory banks without interfering with operation of said core processor.