Methods of forming an interconnect on a semiconductor substrate

• US 5,612,254 A
• Filed: 06/29/1992
• Issued: 03/18/1997
• Est. Priority Date: 06/29/1992
• Status: Expired due to Term

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Sivaram, Srinivasan, Gardner, Donald S., Mu, Xiao-Chun, Fraser, David B.
• Primary Examiner(s): Fourson, George
• Assistant Examiner(s): EVERHART, CARIDAD
• Application Number:
  US07/905,473
• Time in Patent Office: 1,723 Days
• Field of Search: 437/195, 437/225, 437/228, 437/192, 437/194, 437/190, 437/200, 437/229, 148/DIG. 43, 257/758, 257/760, 156/636.1
• US Class Current: 438/634
• CPC Class Codes: H01L 21/76801 characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
• CPC Class Codes: H01L 21/76807 for dual damascene structures
• CPC Class Codes: H01L 21/76843 formed in openings in a dielectric
• CPC Class Codes: H01L 21/76877 Filling of holes, grooves or trenches, e.g. vias, with conductive material
• CPC Class Codes: H01L 2221/1036 Dual damascene with different via-level and trench-level dielectrics
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 23/5329 Insulating materials
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A device and methods of forming an interconnection within a prepatterned channel in a semiconductor device are described. The present invention includes a method of forming an interconnect channel within a semiconductor device. A first dielectric layer is deposited over a substrate and patterned to form a contact opening that is subsequently filled with a contact plug. A second dielectric layer is deposited over the patterned first dielectric layer and the contact plug. The second dielectric layer is patterned to form the interconnect channel, wherein the first dielectric layer acts as an etch stop to prevent etching of the substrate. The present invention also includes a method of forming an interconnect. A dielectric layer is deposited over a substrate and patterned to form an interconnect chapel. A metal layer is deposited over the patterned dielectric layer and within the interconnect channel. The metal layer is polished with an alkaline solution to remove the metal layer that does not lie within the interconnect chapel to form an interconnect. The present invention further includes a method of forming an interconnect over a silicon nitride layer. The silicon nitride layer is deposited over a semiconductor substrate and patterned to form a contact opening that is subsequently filled with a conductive material. A metal layer is deposited on the patterned silicon nitride layer and the contact plug and patterned to form the interconnect such that all of the interconnect lies on the contact plug and part of the patterned silicon nitride layer.

Claims

1. A method of forming an interconnect on a semiconductor substrate comprising the steps of:

depositing a first dielectric layer on said substrate;

patterning said first dielectric layer to form a patterned first dielectric layer having a first opening;

filling said first opening with a conductive plug;

depositing a second dielectric layer over said patterned first dielectric layer and said conductive plug;

patterning said second dielectric layer to form a patterned second dielectric layer having an interconnect channel, wherein part of said interconnect channel lies over at least part of said conductive plug, and wherein at least the upper portion of said first dielectric layer has a lower etch rate than said second dielectric layer such that said first dielectric layer acts as an etch stop;

depositing a barrier layer over said patterned second dielectric layer and within said interconnect channel;

depositing a metal layer over said barrier layer;

polishing said substrate with a polishing solution to remove that portion of said barrier and metal layers that lie on said patterned second dielectric layer to form said interconnect within said interconnect channel; and

depositing a diffusion barrier layer over said patterned second dielectric layer and said interconnect.

2. The method of claim 1, wherein said first and said second dielectric layers comprise a material selected from the group consisting of silicon dioxide, silicon nitride, silicon oxynitride, fluoropolymer, parylene, and polyimide, and wherein said first opening is a type selected from the group consisting of a contact opening and a via opening, said conductive plug is a type selected from the group consisting of a contact plug and a via plug, and said conductive plug comprises a material selected from the group consisting of tungsten, tantalum, titanium nitride, molybdenum, silicide, and polysilicon.

3. The method of claim 1, wherein said barrier layer comprises a material selected from the group consisting of tungsten, tantalum, titanium nitride, niobium, and molybdenum, wherein said metal layer comprises a material selected from the group consisting of aluminum, aluminum alloy, copper, gold, silver, tungsten, and molybdenum, wherein said polishing solution comprises ammonium hydroxide and has a pH in a range of 9-13 and said polishing continues until the surface of said substrate is substantially planar, and wherein said diffusion barrier layer comprises a material selected from the group consisting of silicon nitride, niobium, silicon oxynitride, tantalum, titanium nitride, and molybdenum.

5. The method as described in claim 1 wherein said first dielectric layer comprises a lower layer comprising silicon dioxide and an upper layer comprising silicon nitride, said second dielectric layer comprises silicon dioxide, and wherein said step of patterning said second dielectric layer comprises the steps of:

forming a patterned photoresist layer on said second dielectric layer, said patterned photoresist layer exposing a portion of said second dielectric layer;

etching said exposed portion of said second dielectric layer; and

removing said patterned photoresist layer.

4. A method of forming an interconnect on a semiconductor substrate comprising the steps of:

(A) depositing a first dielectric layer on said substrate;

(B) patterning said first dielectric layer to form a patterned first dielectric layer having a first opening;

(C) filling said first opening with a conductive plug;

(D) depositing a second dielectric layer over said patterned first dielectric layer and said conductive plug;

(E) patterning said second dielectric layer to form a patterned second dielectric layer having said interconnect, wherein part of said interconnect lies over at least part of said conductive plug, wherein at least the upper portion of said first dielectric layer has a lower etch rate than said second dielectric layer such that said first dielectric layer acts as an etch stop, and wherein said first dielectric layer comprises a lower layer comprising silicon dioxide and an upper layer comprising silicon nitride, said second dielectric layer comprises silicon dioxide, and wherein said step of patterning said second dielectric layer comprises the steps of;

(E1) forming a patterned photoresist layer on said second dielectric layer, said patterned photoresist layer exposing a portion of said second dielectric layer;

(E2) etching said exposed portion of said second dielectric layer; and

(E3) removing said patterned photoresist layer;

(F) forming a barrier layer within said interconnect; and

(G) forming a conductive layer over said barrier layer, wherein said barrier layer is a barrier to diffusion of said conductive layer.

19. The method as described in claim 4 wherein said conductive layer comprises copper.

20. The method as described in claim 19 wherein said barrier layer comprises titanium nitride.

6. A method of forming an interconnect on a semiconductor substrate comprising the steps of:

depositing a first dielectric layer on said substrate;

patterning said first dielectric layer to form a first dielectric layer having a first opening;

filling said first opening with a conductive material;

depositing a second dielectric layer on said first dielectric layer and said conductive material, wherein at least the upper portion of said first dielectric layer has a lower etch rate than said second dielectric layer;

patterning said second dielectric layer to form a patterned second dielectric layer having an interconnect channel, at least a portion of said interconnect channel overlying at least a portion of said conductive material;

depositing an interconnect layer by depositing a barrier layer over said patterned second dielectric layer and within said interconnect channel, and depositing a metal layer over said barrier layer, wherein said barrier layer is a barrier to diffusion of said metal layer; and

polishing said substrate with a polishing solution to remove that portion of said interconnect layer that lies on said patterned second dielectric layer to form said interconnect within said interconnect channel.

7. The method of claim 6, wherein said second dielectric layer comprises a material selected from the group consisting of silicon dioxide, silicon nitride, silicon oxynitride, fluoropolymer, parylene, and polyimide, wherein said metal layer comprises a material selected from the group consisting of aluminum, aluminum alloy, copper, gold, silver, tungsten, and molybdenum, and wherein said polishing solution comprises ammonium hydroxide and has a pH in a range of 9-13 and said polishing continues until the surface of said substrate is substantially planar.

8. The method of claim 6 further comprising the steps of:

removing said second dielectric layer after said step of polishing said substrate; and

depositing a diffusion barrier layer over said interconnect.

9. The method of claim 8, wherein said diffusion barrier layer comprises a material selected from the group consisting of silicon nitride, silicon oxynitride, tantalum, titanium nitride, niobium, and molybdenum.

11. The method of claim 9, wherein said first dielectric layer comprises silicon nitride and all of said interconnect lies on at least part of said conductive plug and at least part of said first dielectric layer.

21. The method as described in claim 6 wherein said second dielectric layer comprises silicon dioxide and said metal layer comprises copper.

22. The method as described in claim 21 wherein said barrier layer comprises titanium nitride.

10. A method of forming an interconnect on a semiconductor substrate comprising the steps of:

depositing a first dielectric layer over said substrate;

patterning said first dielectric layer to form a patterned first dielectric layer having a first opening;

filling said first opening with a conductive plug;

depositing a second dielectric layer over said patterned first dielectric layer and said conductive plug;

patterning said second dielectric layer to form a patterned second dielectric layer having an interconnect channel;

depositing a barrier layer over said patterned second dielectric layer and within said interconnect channel;

depositing a conductive layer over said barrier layer, wherein said barrier layer is a barrier to diffusion of said conductive layer;

polishing said substrate with a polishing solution to remove that portion of said barrier and conductive layers that lies on said patterned second dielectric layer to form said interconnect within said interconnect channel; and

depositing a diffusion barrier layer over said interconnect, said conductive layer being encapsulated by said barrier layer and said diffusion barrier layer.

12. The method of claim 10, wherein said first dielectric layer comprises a material selected from the group consisting of silicon dioxide, silicon nitride, silicon oxynitride, fluoropolymer, parylene, and polyimide,

wherein said first opening is a type selected from the group consisting of a contact opening and a via opening, said conductive plug is a type selected from the group consisting of a contact plug and a via plug, and said conductive plug comprises a material selected from the group consisting of tungsten, tantalum, titanium nitride, molybdenum, silicide, and polysilicon,

wherein said second dielectric layer comprises a material selected from the group consisting of silicon dioxide, silicon nitride, silicon oxynitride, fluoropolymer, parylene, and polyimide,

wherein said barrier layer comprises a material selected from the group consisting of tungsten, tantalum, titanium nitride, niobium, and molybdenum,

wherein said conductive layer comprises a material selected from the group consisting of aluminum, aluminum alloy, copper, gold, silver, tungsten, and molybdenum, and

wherein said polishing solution comprises ammonium hydroxide and has a pH in the range of 9-13 and the polishing continues until the surface of said substrate is substantially planar.

13. A method of forming an interconnect on a semiconductor substrate comprising the steps of:

depositing a silicon nitride layer on said substrate;

patterning said silicon nitride layer to form a patterned silicon nitride layer having a first opening;

filling said fast opening with a conductive plug;

depositing a dielectric layer over said patterned silicon nitride layer and said conductive plug;

patterning said dielectric layer to form a patterned dielectric layer having an interconnect channel such that at least part of said interconnect channel lies over at least part of said conductive plug;

depositing an interconnect layer over said patterned dielectric layer and within said interconnect channel;

patterning said interconnect layer to form said interconnect such that said interconnect lies on at least part of said conductive plug and part of said patterned silicon nitride layer;

removing said patterned dielectric layer after said step of patterning said interconnect layer; and

depositing a diffusion barrier layer over said interconnect, said interconnect being encapsulated by said patterned silicon nitride layer, said conductive plug, and said diffusion barrier layer.

14. The method of claim 13, herein said dielectric layer comprises a material selected from the group consisting of silicon dioxide, silicon nitride, silicon oxynitride, fluoropolymer, parylene, and polyimide, wherein said first opening is a type selected from the group consisting of a contact opening and a via opening, said conductive plug is a type selected from the group consisting of a contact plug and a via plug, and said conductive plug comprises a material selected from the group consisting of tungsten, tantalum, titanium nitride, molybdenum, silicide, and polysilicon, and wherein said interconnect layer comprises a material selected from the group consisting of aluminum, aluminum alloy, copper, gold, silver, tungsten and molybdenum.

15. The method of claim 14, wherein said diffusion barrier layer comprises a material selected from the group consisting of silicon nitride, silicon oxynitride, tantalum, titanium nitride, and molybdenum.

16. A method of forming an interconnect on a semiconductor substrate comprising the steps of:

depositing a silicon nitride layer on said substrate;

patterning said silicon nitride layer to form a patterned silicon nitride layer having a first opening;

filling said first opening with a conductive plug;

depositing a dielectric layer over said patterned silicon nitride layer and said conductive plug;

patterning said dielectric layer to form a patterned dielectric layer having an interconnect channel such that at least part of said interconnect channel lies over at least part of said conductive plug;

depositing an interconnect layer over said patterned dielectric layer and within said interconnect channel; and

patterning said interconnect layer to form said interconnect such that said interconnect lies on at least part of said conductive plug and part of said patterned silicon nitride layer, wherein said step of depositing said interconnect layer comprises the steps of;

depositing a barrier layer over said patterned dielectric layer and within said interconnect channel; and

depositing a metal layer over said barrier layer.

17. The method of claim 16 further comprising the step of depositing a diffusion barrier layer over said patterned dielectric layer and said interconnect, said metal layer being encapsulated by said barrier layer and said diffusion barrier layer.

18. The method of claim 17, wherein said barrier layer comprises a material selected from the group consisting of tungsten, tantalum, titanium nitride, niobium, and molybdenum,

wherein said metal layer comprises a material selected from the group consisting of aluminum, aluminum alloy, copper, gold, silver, tungsten and molybdenum, and

wherein said diffusion barrier layer comprises a material selected from the group consisting of silicon nitride, silicon oxynitride, tantalum, titanium nitride, niobium, and molybdenum.