Multi-layer electrical interconnection structures and fabrication methods

• US 5,612,256 A
• Filed: 02/10/1995
• Issued: 03/18/1997
• Est. Priority Date: 02/10/1995
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Display Technology, Inc. (PixTech, Inc.)
• Inventors: Stansbury, Darryl M.
• Primary Examiner(s): PICARDAT, KEVIN M
• Application Number:
  US08/386,644
• Time in Patent Office: 767 Days
• Field of Search: 437/209, 437/211, 437/214, 437/215, 437/216, 437/217, 437/218, 361/760, 361/761, 361/762, 361/763, 361/764, 361/765, 257/778
• US Class Current: 438/20
• CPC Class Codes: H01J 2329/00 Electron emission display panels, e.g. field emission display panels
• CPC Class Codes: H01J 2329/8625 Spacing members
• CPC Class Codes: H01J 2329/92 Means forming part of the display panel for the purpose of providing electrical connection to it
• CPC Class Codes: H01J 29/028 Mounting or supporting arrangements for flat panel cathode ray tubes, e.g. spacers particularly relating to electrodes
• CPC Class Codes: H01J 29/92 Means forming part of the tube for the purpose of providing electrical connection to it
• CPC Class Codes: H01J 9/185 of flat panel display devices, e.g. by using spacers
• CPC Class Codes: H01J 9/241 the vessel being for a flat panel display H01J9/261 takes precedence; flat discharge lamps H01J9/248
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45124 Aluminium (Al) as principal constituent
• CPC Class Codes: H01L 2224/48465 the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
• CPC Class Codes: H01L 2224/78 Apparatus for connecting with wire connectors
• CPC Class Codes: H01L 2224/85 using a wire connector
• CPC Class Codes: H01L 24/45 of an individual wire connector
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/85 using a wire connector wire bonding in general B23K20/004
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01013 Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01049 : Indium [In]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/20753 : larger or equal to 30 microns less than 40 microns
• CPC Class Codes: Y10T 29/49144 : by metal fusion
• CPC Class Codes: Y10T 29/49162 : by using wire as conductive path

Abstract

A flat-panel field emission display comprises a luminescent faceplate, a rigid backplate, and an interposed or sandwiched emitter or cathode plate. A dielectric connector ridge is screen-printed over the faceplate'"'"'s rear surface. Upper and lower level conductors are then screen printed over the faceplate. The lower-level conductors are applied directly on the faceplate rear surface. The upper-level conductors are applied atop the connector ridge. A plurality of bond wire interconnections extend between individual screen-printed conductors of the upper and lower levels. The bond wire interconnections create inter-level electrical interconnections between said individual screen-printed conductors. The cathode plate is positioned over the connector ridge. The cathode plate has a plurality of die bond pads facing the faceplate rear surface and aligned with the upper-level conductors. A plurality of conductive bonds such as flip-chip connections are positioned between the die bond pads and the facing upper-level conductors.

Claims

1. A method of fabricating a multi-layer electrical interconnection structure comprising:

screen printing a plurality of conductors over a substrate at upper and lower levels;

wire bonding between individual screen-printed conductors of the upper and lower levels to create inter-level electrical connections between said individual screen-printed conductors of the upper and lower levels; and

further comprising;

positioning a semiconductor die over the substrate, the semiconductor die having die bond pads which face the substrate;

aligning individual die bond pads to said individual upper-level screen-printed conductors;

making wedge bonds either to said individual die bond pads or to said individual upper-level screen-printed conductors with bond wire from a wire bonder;

leaving projecting tails of bond wire from individual wedge bonds, the bond wire tails being interposed between said individual die bond pads and said individual upper-level screen-printed conductors; and

pressing the semiconductor die against the substrate, the projecting tails forming conductive bonds between said individual aligned die bond pads and said individual upper-level screen-printed conductors.

2. A method of fabricating a multi-layer electrical interconnection structure, comprising:

screen printing a dielectric layer over a substrate;

screen printing a lower level of conductors on the substrate at a first elevation;

screen printing an upper level of conductors atop the dielectric layer at a second elevation which is greater than the first elevation;

wire bonding between individual screen-printed conductors of the upper and lower levels to create inter-level electrical connections between said individual screen-printed conductors of the upper and lower levels; and

further comprising;

positioning a semiconductor die over the substrate, the semiconductor die having a plurality of die bond pads facing the substrate;

aligning the die bond pads to said individual upper-level screen-printed conductors;

making wedge bonds either to the die bond pads or to said individual upper-level screen-printed conductors with bond wire from a wire bonder; and

leaving projecting tails of bond wire from individual wedge bonds, the bond wire tails being interposed between the die bond pads and said individual upper-level screen-printed conductors to conductively bond therebetween.

3. A method of fabricating a multi-layer interconnection structure, the method comprising:

forming a dielectric connector ridge over a planar substrate;

forming a lower level of conductors on the substrate;

forming an upper level of conductors atop the connector ridge;

wire bonding between individual conductors of the upper and lower levels to create inter-level electrical connections therebetween;

positioning a semiconductor die over the connector ridge, the semiconductor die having a plurality of die bond pads facing the substrate;

conductively bonding the bond pads of the semiconductor die to said individual upper-level conductors;

and further comprising;

making wedge bonds either to the die bond pads or to said individual upper-level conductors with bond wire from a wire bonder; and

leaving projecting tails of bond wire from individual wedge bonds, the bond wire tails being interposed between the die bond pads and said individual upper-level conductors to conductively bond therebetween.

4. A method of fabricating a multi-layer electrical interconnection structure comprising:

screen printing a plurality of conductors over a substrate at upper and lower levels;

wire bonding between individual screen-printed conductors of the upper and lower levels to create inter-level electrical connections between said individual screen-printed conductors of the upper and lower levels; and

further comprising;

positioning a semiconductor die over the substrate, the semiconductor die having die bond pads which face the substrate;

aligning individual die bond pads to said individual upper-level screen-printed conductors;

providing a projecting tail of a conductor from either at least one of said individual die bond pads or from at least one of said individual upper-level screen-printed conductors, said projecting tail being interposed between said at least one individual die bond pad and said at least one individual upper-level screen-printed conductor; and

pressing the semiconductor die against the substrate, the projecting conductor tail forming a conductive bond between said at least one individual aligned die bond pad and said at least one individual upper-level screen-printed conductor.

5. A method of fabricating a multi-layer electrical interconnect structure, comprising the steps of:

providing a substrate having an upper level and a lower level;

forming a plurality of conductors over said substrate, a first portion of the plurality of conductors located on said upper level of said substrate and a second portion of said plurality of conductors located on said lower level of said substrate, said plurality of conductors being formed substantially at the same time on said upper level and said lower level of said substrate; and

forming a plurality of wire bonds between conductors of said first portion and said second portion, individual of said wire bonds extending between a respective conductor of said first portion and a respective conductor of said second portion.

6. A method of fabricating a multi-layer electrical interconnect structure, comprising the steps of:

forming a substrate having an upper level and a lower level;

generally simultaneously forming a first plurality of conductors on said upper level of said substrate and a second plurality of conductors on said lower level of said substrate; and

forming a plurality of wire bond interconnects, each wire bond interconnect extending between at least one conductor on said upper level of said substrate and at least one conductor on said lower level of said substrate.

7. A method of fabricating a multi-layer electrical interconnection structure, comprising the steps of:

providing a substrate having an upper level and a lower level, said substrate formed substantially of a generally dielectric material;

forming a first plurality of conductors on said upper level of said substrate and a second plurality of conductors on said lower level of said substrate, said first and second pluralities of conductors being formed in a substantially continuous process; and

forming a plurality of wire interconnects between selected conductors of said plurality of conductors and said second plurality of conductors.

8. A method of fabricating a field emission display, comprising the steps of:

providing a substrate, said substrate having an upper level and a lower level;

forming a plurality of conductors on said substrate, with at least a first conductor located on said upper level of said substrate and a second conductor located on said lower level of said substrate;

forming a wire bond interconnection between said first conductor and said second conductor; and

placing a die having emitter tips and conductive pads thereon over the substrate, with at least one conductive pad being in electrical contact with said first conductor.

9. A method of fabricating a field emission display, comprising the steps of:

providing a first member, said first member including a dielectric member having first and second levels;

forming a first group of conductors on said first level of said dielectric member;

forming a second group of conductors on said second level of said dielectric member; and

forming a plurality of wire interconnects between individual conductors of said first and second groups of conductors.

10. A method of forming a field emission display, comprising the steps of:

providing a substrate having an elevated connector surface formed thereon;

forming a first level of conductors on said substrate;

forming a second level of conductors on said elevated connector surface;

wire bonding individual conductors between selected conductors on said substrate and conductors on said elevated connector surface;

providing a semiconductor die;

positioning said semiconductor die proximate said elevated connector surface, said semiconductor die having a plurality of bond pads facing said substrate; and

bonding said bond pads of said semiconductor die to individual conductors of said second level of conductors.

11. A method of fabricating a field emission display, comprising the steps of:

providing a substrate comprising an outer surface;

forming a substantially inflexible dielectric layer over the substrate outer surface, the dielectric layer defining an upper level and the outer surface defining a lower level;

forming a plurality of conductors on said outer surface and dielectric layer, with at least a first conductor located on said upper level and a second conductor located on said lower level;

forming a wire bond interconnection between said first conductor and said second conductor; and

placing a die having emitter tips and conductive pads thereon over the substrate, with at least one conductive pad being in electrical contact with said first conductor.

12. A method of fabricating a field emission display, comprising the steps of:

providing a first member having a substantially inflexible dielectric member formed thereon, said first member defining a first level, said dielectric member thereon defining a second level;

forming a first group of conductors on said first level and a second group of conductors on said second level; and

forming a plurality of wire interconnects between individual conductors of said first and second groups of conductors.

13. A method of forming a field emission display, comprising the steps of:

providing a first member having a substantially inflexible dielectric member formed thereon, said first member defining a first level, said dielectric member thereon defining a second elevated connector level;

forming a first level of conductors on said first member;

forming a second level of conductors on said elevated connector level;

wire bonding individual conductors between selected conductors on said first member and conductors on said elevated connector level;

providing a semiconductor die;

positioning said semiconductor die proximate said elevated connector level, said semiconductor die having a plurality of bond pads facing said first member and dielectric member; and

bonding said bond pads of said semiconductor die to individual conductors of said second elevated level of conductors.