Article and method of manufacturing an enclosed electrical circuit using an encapsulant

• US 5,612,513 A
• Filed: 09/19/1995
• Issued: 03/18/1997
• Est. Priority Date: 09/19/1995
• Status: Expired due to Term

• Current Assignee: Round Rock Research LLC
• Original Assignee: Micron Communications, Inc. (Micron Technology, Inc.)
• Inventors: Tuttle, Mark E., Lake, Rickie C., Cirino, Clay L., Mousseau, Joe P.
• Primary Examiner(s): Thomas, Laura
• Application Number:
  US08/530,747
• Time in Patent Office: 546 Days
• Field of Search: 257/787, 257/782, 257/783, 257/784, 174/255, 174/256, 174/250, 174/258, 174/260, 361/756, 361/749, 361/765, 29/841, 29/832
• US Class Current: 174/260
• CPC Class Codes: H01L 2223/6677 for antenna, e.g. antenna included within housing of semiconductor device antennas per se H01Q
• CPC Class Codes: H01L 2224/81 using a bump connector
• CPC Class Codes: H01L 2224/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 23/24 solid or gel at the normal operating temperature of the device H01L23/3135 takes precedence
• CPC Class Codes: H01L 23/5387 Flexible insulating substrates H01L23/5388 takes precedence
• CPC Class Codes: H01L 23/58 Structural electrical arrangements for semiconductor devices not otherwise provided for , e.g. in combination with batteries H01L23/49593, H01L23/49596 take precedence
• CPC Class Codes: H01L 24/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 25/0655 the devices being arranged next to each other
• CPC Class Codes: H01L 25/50 Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01027 Cobalt [Co]
• CPC Class Codes: H01L 2924/01033 Arsenic [As]
• CPC Class Codes: H01L 2924/01047 Silver [Ag]
• CPC Class Codes: H01L 2924/01082 Lead [Pb]
• CPC Class Codes: H01L 2924/14 Integrated circuits
• CPC Class Codes: H01L 2924/19043 being a resistor
• CPC Class Codes: H05K 1/189 characterised by the use of a flexible or folded printed circuit H05K3/326 takes precedence
• CPC Class Codes: H05K 3/284 for encapsulating mounted components H05K1/185 takes precedence
• CPC Class Codes: Y10T 29/4913 Assembling to base an electrical component, e.g., capacitor, etc.
• CPC Class Codes: Y10T 29/49146 : with encapsulating, e.g., potting, etc.

Abstract

An enclosed electrical circuit and method for manufacturing the electrical circuit are provided. Initially a flexible substrate is formed with a plurality of electrical circuits. By way of example, each circuit can contain a conductive trace, a battery and a die, all in electrical communication. During the manufacturing process, a barrier is placed on the substrate and a curable encapsulant is poured into a cavity formed by the barrier and the substrate to encapsulate each circuit. The barrier can be formed as a compartmentalized dam having a separate cavity for each circuit, as a perimeter dam having a single cavity, or as a spacer sheet having a separate cavity for each circuit formed by a pattern of cut outs. Following the encapsulation step, the electrical circuits can be singulated into separate encapsulated circuits.

Claims

1. A method for manufacturing an encapsulated electrical circuit comprising:

forming a substrate;

forming an image on a surface of the substrate viewable through the substrate;

forming the circuit on the surface;

forming a barrier on the substrate to define a cavity surrounding the circuit; and

placing an encapsulant in the cavity.

2. The method as claimed in claim 1 and further comprising:

mounting a die on the surface in electrical communication with the circuit; and

mounting a battery on the surface in electrical communication with the circuit.

3. The method claimed in claim 1 and wherein the substrate is substantially transparent and the image comprises an ink layer applied to the surface.

4. The method as claimed in claim 1 and wherein the encapsulant comprises an epoxy in a viscous state when placed in the cavity and further comprising the step of curing the epoxy.

5. The method as claimed in claim 1 and further comprising applying a releasing agent to the barrier to allow separation of the barrier and encapsulant.

6. The method as claimed in claim 1 and wherein the barrier comprises a spacer sheet having the cavity formed as a cut out.

7. The method as claimed in claim 1 further comprising covering the encapsulant with a flexible cover.

8. A method for manufacturing an electrical circuit comprising:

forming a substrate;

forming a plurality of conductive traces on the substrate;

mounting electrical components on the substrate in electrical communication with the conductive traces to form a plurality of separate circuits;

placing a spacer sheet on the substrate comprising a plurality of separate cavities for the separate circuits;

depositing a curable compound into the cavities to encapsulate each of the separate circuits;

curing the compound; and

singulating the substrate and spacer sheet to form a plurality separate encapsulated circuits.

9. The method as claimed in claim 8 and wherein the mounting step comprises:

mounting a die on the substrate for each separate circuit; and

mounting a battery on the substrate for each separate circuit.

10. The method as claimed in claim 8 and further comprising covering the encapsulant with a flexible cover.

11. The method as claimed in claim 8 wherein the singulating step comprises a method selected from the group consisting of cutting, shearing and routering.

12. The method as claimed in claim 8 and wherein the conductive traces are formed by screen printing.

13. The method as claimed in claim 8 and further comprising forming the substrate of a substantially transparent material and forming an image on a surface of the substrate wherein the circuits are formed.

14. The method as claimed in claim 8 and further comprising forming the substrate of a transparent material and forming a reverse image on a surface of the substrate wherein the circuits are formed.

15. The method as claimed in claim 8 and further comprising forming a portion of the conductive trace as an antenna.

16. The method as claimed in claim 8 and further comprising forming an antenna on the substrate in electrical communication with the conductive trace.

17. An encapsulated circuit comprising:

a transparent flexible substrate;

an image formed on a surface of the substrate;

an electrical circuit formed on the surface; and

an encapsulating layer covering the surface and the electrical circuit.

18. The encapsulated circuit as claimed in claim 17 and wherein the image comprises an ink layer.

19. The encapsulated circuit as claimed in claim 17 and wherein the electrical circuit comprises:

a conductive trace formed on the substrate;

a die mounted on the substrate in electrical communication with the trace;

a battery mounted on the substrate in electrical communication with the trace.

20. The encapsulated circuit as claimed in claim 19 wherein a positive terminal and a negative terminal of the battery are co-planar.

21. The encapsulated circuit as claimed in claim 17 wherein the encapsulating layer comprises a curable epoxy.

22. The encapsulated circuit as claimed in claim 17 wherein the encapsulating layer comprises an opaque material.

23. The encapsulated circuit as claimed in claim 17 and wherein the circuit comprises a die and a battery.

24. The encapsulated circuit as claimed in claim 23 wherein the die and battery are mounted to the substrate using a conductive adhesive.

25. The encapsulated circuit as claimed in claim 17 and further comprising a flexible cover formed on the encapsulant.

26. An encapsulated circuit comprising:

a transparent flexible substrate;

an electrical circuit formed on the substrate;

an ink layer applied to the substrate between the substrate and the electrical circuit to provide an image visible through the substrate; and

an encapsulating layer covering the substrate and the electrical circuit with the electrical circuit encapsulated between the substrate and encapsulating layer.

27. The encapsulated circuit as claimed in claim 26 and wherein the electrical circuit comprises:

a conductive trace formed on the substrate;

a die mounted on the substrate in electrical communication with the trace;

a battery having a positive terminal and a negative terminal in electrical communication with the trace.

28. The encapsulated circuit as claimed in claim 26 and wherein the die and the battery are mounted on the substrate using a conductive adhesive.

29. A method for manufacturing an encapsulated electrical circuit comprising:

forming a substrate;

forming a plurality of circuits on the substrate;

placing a barrier on the substrate to define a single cavity surrounding the circuits;

forming an encapsulant in the cavity to encapsulate the circuits;

separating the barrier from the encapsulant; and

separating the encapsulated circuit from a remainder of the circuits.

30. The method as claimed in claim 29 and further comprising applying a releasing agent to the barrier to facilitate separating the barrier from the substrate.

31. The method as claimed in claim 29 and wherein each circuit includes a battery, a semiconductor die and an antenna.

32. A method for manufacturing an encapsulated electrical circuit comprising:

forming a substrate;

forming a plurality of circuits on the substrate;

providing a compartmental dam comprising an opening for each of the circuits;

placing the dam on the substrate;

forming an encapsulant in the cavities to encapsulate the circuits;

separating the dam from the substrate; and

separating the encapsulated circuit from a remainder of the circuits.

33. The method as claimed in claim 32 and further comprising applying a releasing agent to the dam to facilitate separating the dam from the substrate.

34. The method as claimed in claim 32 and wherein each circuit includes a battery, a semiconductor die and an antenna.