Vertically stacked vertical transistors used to form vertical logic gate structures

• US 5,612,563 A
• Filed: 01/25/1994
• Issued: 03/18/1997
• Est. Priority Date: 03/02/1992
• Status: Expired due to Fees

• Current Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Witek, Keith E., Mazure, Carlos A., Fitch, Jon T.
• Primary Examiner(s): LOKE, STEVEN HO YIN
• Application Number:
  US08/186,872
• Time in Patent Office: 1,148 Days
• Field of Search: 257/329, 257/330, 257/331, 257/368, 257/369, 257/66
• US Class Current: 257/329
• CPC Class Codes: H01L 21/76897 Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step self-aligned silicidation on field effect transistors H01L29/665
• CPC Class Codes: H01L 21/8221 Three dimensional integrated circuits stacked in different levels
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/6675 Amorphous silicon or polysilicon transistors
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence
• CPC Class Codes: H01L 29/7834 with a non-planar structure, e.g. the gate or the source or the drain being non-planar

Abstract

A transistor (10) has a substrate (12) and a diffusion (14). A gate conductive layer (18) overlies the substrate (12) and has a sidewall formed by an opening that exposes the substrate (12). A sidewall dielectric layer (22) formed laterally adjacent the conductive layer (18) sidewall functions as a gate dielectric for the transistor (10). A conductive region is formed within the opening. The conductive region has a first current electrode region (28) and a second control electrode region (34) and a channel region (30) laterally adjacent the sidewall dielectric layer (22). A plurality of transistors, each in accordance with transistor (10), can be stacked in a vertical manner to form logic gates such as NMOS or PMOS NAND, NOR, and inverter gates, and/or CMOS NAND, NOR, and inverter gates with one or more inputs.

Claims

1. A transistor structure comprising:

plurality of M stacked transistors, where M is an integer, each of the M stacked transistors having;

a base layer having a surface;

a first dielectric layer overlying the base layer;

a control electrode conductive layer overlying the first dielectric layer;

a second dielectric layer overlying the control electrode conductive layer;

a device opening formed through each of the first dielectric layer, the control electrode conductive layer, and the second dielectric layer to expose the base layer, the device opening separating the control electrode conductive layer into N control electrode(s) where N is an integer, each of the N control electrode(s), having a sidewall;

a sidewall dielectric formed laterally adjacent each sidewall of the N control electrode(s),

a first current electrode formed within the device opening and overlying the base layer;

a channel region formed within the device opening, laterally adjacent each sidewall dielectric of the N control electrode(s), and overlying the first current electrode;

a second current electrode formed overlying the channel region; and

wherein each of the M stacked transistors have N control electrode(s) where N is a finite positive integer, each of the M stacked transistors, except an Mth top transistor which overlies all other M stacked transistors, having a second current electrode thereof electrically coupled to a first current electrode of an immediately overlying transistor, the transistor structure having an output conductor for providing an output signal, the output conductor being coupled to one second current electrode of one of the M stacked transistors wherein the one of the M stacked transistors is any of the M stacked transistors except the Mth top transistor which overlies all other M stacked transistors.

2. The transistor structure of claim 1 wherein a first transistor in the M stacked transistors is an N-channel transistor and a second transistor in the M stacked transistors is a P-channel transistor.

3. The transistor structure of claim 1 further comprising:

a first transistor and a second transistor which comprise the M stacked transistors where M is two, the first transistor underlying the second transistor and having a first control electrode and a second control electrode where N is two for the first transistor, and the second transistor having a control electrode wherein N is one for the second transistor;

a first conductor coupling the first current electrode of the first transistor to a reference voltage terminal;

a second conductor coupling the second current electrode of the second transistor to a power supply terminal;

the output conductor coupled either to the second current electrode of the first transistor or the first current electrode of the second transistor;

a first input conductor coupled to the first control electrode of the first transistor; and

a second input conductor coupled to the second control electrode of the first transistor for the formation of a NOR logic gate.

4. The transistor structure of claim 1 further comprising:

a first transistor, a second transistor, and a third transistor which comprise the M stacked transistors where M is three, the first transistor underlying the second transistor, the second transistor underlying the third transistor, and each of the first, second, and third transistors having at least one control electrode where N is greater than one for the third transistor;

a first conductor coupling the first current electrode of the first transistor to a reference voltage terminal;

a second conductor coupling the second current electrode of the third transistor to a power supply terminal;

the output conductor electrically coupled to both the second current electrode of the second transistor and the first current electrode of the third transistor;

a first input conductor coupled to a control electrode of the first transistor; and

a second input conductor coupled to a control electrode of the second transistor for the formation of a NAND logic gate.

5. The transistor structure of claim 1 further comprising:

a first transistor and a second transistor which comprise the M stacked transistors where M is two, the first transistor underlying the second transistor, and each of the first and second transistors having a single control electrode where N is one for the first and second transistors, the second current electrode of the first transistor being coupled to the first current electrode of the second transistor to define an output node region;

a first conductor coupling the first current electrode of the first transistor to a reference voltage terminal;

a second conductor coupling the second current electrode of the second transistor to a power supply terminal;

the output conductor coupled to the output node region for providing an output signal; and

an input conductor coupled to the control electrode of the first transistor to complete formation of an inverter logic gate.

6. The transistor structure of claim 1 further comprising:

a first transistor, a second transistor, and a third transistor which comprise the M stacked transistors where M is three, the first transistor underlying the second transistor, the second transistor underlying the third transistor, the first transistor having a first control electrode and a second control electrode where N is two for the first transistor, and the second and third transistors each having a control electrode where N is one for the second and third transistors;

a first conductor coupling the first current electrode of the first transistor to a reference voltage terminal;

a second conductor coupling the second current electrode of the third transistor to a power supply terminal;

the output conductor coupled to the second current electrode of the first transistor and the first current electrode of the second transistor;

a first input conductor coupled to the first control electrode of the first transistor;

a second input conductor coupled to the second control electrode of the first transistor; and

routing wherein either the first input conductor is coupled to the control electrode of the third transistor and the second input conductor is coupled to the control electrode of the second transistor or the second input conductor is coupled to the control electrode of the third transistor and the first input conductor is coupled to the control electrode of the second transistor to complete formation of a NOR logic gate.

7. The transistor structure of claim 1 further comprising:

a first transistor, a second transistor, and a third transistor which comprise the M stacked transistors where M is three, the first transistor underlying the second transistor, the second transistor underlying the third transistor, each of the first and second transistors having a control electrode where N is one for the first and second transistors, and the third transistor having a first control electrode and a second control electrode where N is two for the third transistor;

a first conductor coupling the first current electrode of the first transistor to a reference voltage terminal;

a second conductor coupling the second current electrode of the third transistor to a power supply terminal;

the output conductor coupled to the second current electrode of the second transistor and the first current electrode of the third transistor;

a first input conductor coupled to the first control electrode of the third transistor;

a second input conductor coupling the second control electrode of the third transistor; and

routing wherein either the first input conductor is coupled to the control electrode of the first transistor and the second input conductor is coupled to the control electrode of the second transistor or the second input conductor is coupled to the control electrode of the first transistor and the first input conductor is coupled to the control electrode of the second transistor to complete formation of a NAND logic gate.

8. The transistor structure of claim 1 further comprising:

a first transistor and a second transistor which comprise the M stacked transistors where M is two, the first transistor underlying the second transistor, and each of the first and second transistors having a control electrode where N is one for the first and second transistors, the second current electrode of the first transistor being coupled to the first current electrode of the second transistor to define an output node region;

a first conductor coupling the first current electrode of the first transistor to a reference voltage terminal;

a second conductor coupling a second current electrode of the second transistor to a power supply terminal;

the output conductor coupled the output node region to provide an output signal; and

an input conductor coupling the control electrodes of the first and second transistors to complete formation of an inverter logic gate.

9. The transistor structure of claim 1 further comprising:

a first transistor and a second transistor which comprise the M stacked transistors where M is two, the first transistor underlying the second transistor, the second transistor having a first control electrode and a second control electrode where N is two for the second transistor, and the first transistor having a control electrode where N is one for the first transistor;

a first conductor coupling the first current electrode of the first transistor to a power supply terminal;

a second conductor coupling the second current electrode of the second transistor to a reference voltage terminal;

the output conductor coupled to either the second current electrode of the first transistor or the first current electrode of the second transistor;

a first input conductor coupled to the first control electrode of the second transistor; and

a second input conductor coupled to the second control electrode of the second transistor for the formation of a NOR logic gate.

10. The transistor structure of claim 1 further comprising:

a first transistor, a second transistor, and a third transistor which comprise the M stacked transistors where M is three, the first transistor underlying the second transistor, the second transistor underlying the third transistor, and each of the first, second, and third transistors having a control electrode where N is at least one for the first, second, and third transistors, the first current electrode of an L stacked transistor, where L is an integer within the range of 2 through M, being coupled to the second current electrode of an (L-1) stacked transistor to form an output node;

a first conductor coupling the first current electrode of the first transistor to a power supply terminal;

a second conductor coupling the second current electrode of the third transistor to a reference voltage terminal;

the output conductor coupled to the output node to provide an output signal;

a first input conductor coupled to the control electrode of the second transistor; and

a second input conductor coupled to one of the at least one control electrode of the third transistor for the formation of a NAND logic gate.

11. The transistor structure of claim 1 further comprising:

a first transistor and a second transistor which comprise the M stacked transistors where M is two, the first transistor underlying the second transistor, and each of the first and second transistors having a control electrode where N is one for the first and second transistors, the first current electrode of the second transistor being coupled to the second current electrode of the first transistor to define an output node;

a first conductor coupling the first current electrode of the first transistor to a power supply terminal;

a second conductor coupling the second current electrode of the second transistor to a reference voltage terminal;

the output conductor coupled to the output node for providing an output signal; and

an input conductor coupling the control electrodes of the first and second transistors to complete formation of an inverter logic gate.

12. The transistor structure of claim 1 further comprising:

a first transistor, a second transistor, and a third transistor which comprise the M stacked transistors where M is three, the first transistor underlying the second transistor, the second transistor underlying the third transistor, the third transistor having a first control electrode and a second control electrode where N is two for the third transistor, and the first and second transistors each having a control electrode;

a first conductor coupling the first current electrode of the first transistor to a power supply terminal;

a second conductor coupling the second current electrode of the third transistor to a reference voltage terminal;

the output conductor coupled to the second current electrode of the second transistor and the first current electrode of the third transistor;

a first input conductor coupled to the first control electrode of the third transistor;

a second input conductor coupled to the second control electrode of the third transistor; and

routing wherein either the first input conductor is coupled to the control electrode of the first transistor and the second input conductor is coupled to the control electrode of the second transistor or the second input conductor is coupled to the control electrode of the first transistor and the first input conductor is coupled to the control electrode of the second transistor to complete formation of a NOR logic gate.

13. The transistor structure of claim 1 further comprising:

a first transistor, a second transistor, and a third transistor which comprise the M stacked transistors wherein M is three, the first transistor underlying the second transistor, the second transistor underlying the third transistor, each of the second and third transistors having a control electrode where N is one for the second and third transistors, and the first transistor having a first control and a second control electrode where N is two for the first transistor;

a first conductor coupling the first current electrode of the first transistor to a power supply terminal;

a second conductor coupling the second current electrode of the third transistor to a reference voltage terminal;

the output conductor coupled to the second current electrode of the first transistor and the first current electrode of the second transistor;

a first input conductor coupled to the first control electrode of the first transistor;

a second input conductor coupled to the second control electrode of the first transistor; and

routing wherein either the first input conductor is coupled to the control electrode of the third transistor and the second input conductor is coupled to the control electrode of the second transistor or the second input conductor is coupled to the control electrode of the third transistor and the first input conductor is coupled to the control electrode of the second transistor to complete formation of a NAND logic gate.

14. The transistor structure of claim 1 further comprising:

a first transistor and a second transistor which comprise the M stacked transistors where M is two, the first transistor underlying the second transistor wherein one of the first transistor or the second transistor is an N-channel transistor and a remaining transistor of the first and second transistors is a P-channel transistor, each of the first and second transistors having a control electrode where N is one for the first and second transistors, the first current electrode of the second transistor being coupled to the second current electrode of the first transistor to form an output node;

a first conductor coupling the first current electrode of the first transistor to a first power supply terminal;

a second conductor coupling the second current electrode of the second transistor to a second power supply terminal;

the output conductor coupled to the output node for providing an output signal; and

an input conductor coupling the control electrodes of the first and second transistors to complete formation of a CMOS inverter logic gate.

15. The transistor structure of claim 1 further comprising:

a first transistor, a second transistor, and a third transistor which comprise the M stacked transistors where M is three, the first transistor underlying the second transistor, the second transistor underlying the third transistor, and each of the first, second, and third transistors having at least one control electrode where N is greater than one for the first transistor;

a first conductor coupling the first current electrode of the first transistor to a power supply terminal;

a second conductor coupling the second current electrode of the third transistor to a reference voltage terminal;

the output conductor electrically coupled to both the second current electrode of the first transistor and the first current electrode of the second transistor;

a first input conductor coupled to a control electrode of the first transistor; and

a second input conductor coupled to a control electrode of the second transistor for the formation of a NAND logic gate.

16. A logic device comprising:

a substrate having a top-most surface;

a plurality of N rank ordered stacked transistors, where N is an integer, each transistor except a first transistor thereof overlying a transistor of immediately lower rank, each transistor having a first current electrode, a second current electrode, and at least one control electrode wherein for each of the stacked transistors either the first current electrode overlies the second current electrode thereof or the second current electrode overlies the first current electrode thereof where the first and second current electrodes are separated by a channel region, the plurality of N rank ordered stacked transistors being at least partially surrounded by both dielectric insulation material and gate dielectric material, a channel region of at least one of the transistors in the plurality of rank ordered stacked transistors overlying the top-most surface of the substrate;

gate conductors, which are surrounded by the dielectric insulation material and overlie the top-most surface of the substrate, are coupled to each control electrode within the plurality of stacked transistors to provide control voltages to the transistors to alter a current flow through the channel regions; and

an output conductor coupled to a predetermined current electrode within the N rank ordered stacked transistors, the output conductor being surrounded by the dielectric insulation material, wherein at least one of the transistors has at least two independent control electrodes.

17. The logic device of claim 16 wherein the output conductor selectively provides both a logic level one and a logic level zero out from the transistors in mutually exclusive time intervals.

18. The logic device of claim 16 wherein a top-most current electrode of the N rank ordered stacked transistors is coupled to the first power supply conductor and a lowest-most current electrode of the N rank ordered stacked transistors is coupled to the second power supply conductor wherein the second power supply conductor provides a voltage potential having a different value than the first power supply conductor.

19. A logic device comprising:

a substrate having a top surface;

a first vertical transistor having a first current electrode coupled to a first power supply conductive region, a second current electrode overlying the first current electrode, a channel region separating the first current electrode and the second current electrode, a gate dielectric layer having a first side and a second side wherein the first side is abutting the channel region and the second side is abutting at least one gate electrode wherein the gate dielectric layer separates the channel region and the at least one gate electrode; and

a second vertical transistor overlying the first vertical transistor, the second vertical transistor having a first current electrode coupled to the second current electrode of the first vertical transistor, a second current electrode overlying the first current electrode of the second transistor, the second current electrode being coupled to a second power supply conductive region, a channel region separating the first current electrode and the second current electrode, a gate dielectric layer having a first side and a second side wherein the first side is abutting the channel region and the second side is abutting at least one gate electrode wherein the gate dielectric layer separates the channel region and the at least one gate electrode, the second current electrode of the second vertical transistor overlying the top surface of the substrate;

an output conductive layer coupled to a location between the first and second transistors, the output conductive layer providing an output signal from the first and second transistors and being isolated by dielectric material and overlying the top surface of the substrate, the logic device having one logical output provided via the output conductive layer and at least two logical inputs.

20. The logic device of claim 19 wherein a metallic silicide region is between the first current electrode of the second transistor and the second current electrode of the first transistor to reduce diode voltage drops across the first current electrode of the second transistor and the second current electrode of the first transistor.

21. The logic device of claim 19 wherein the first and second transistors are coupled to form a logic device selected from a group consisting of:

an AND gate, and a NAND gate.

22. The logic device of claim 19 wherein the first and second transistors are coupled to form a logic device selected from a group consisting of:

an OR gate, and a NOR gate.

23. The logic device of claim 19 wherein the first vertical transistor is an N channel transistor and the second vertical transistor is a P channel transistor.

24. The logic device of claim 19 wherein the first vertical transistor is a P channel transistor and the second vertical transistor is an N channel transistor.

26. The logic device of claim 19 wherein the second current electrode of the first vertical transistor is connected to the first current electrode of the second vertical transistor by a metallic region so that a voltage drop between the first current electrode of the second vertical transistor and the second current electrode of the first vertical transistor is substantially equal to zero.

27. The logic device of claim 19 wherein the first power supply conductive region is coupled to a ground potential and the second power supply conductive region is coupled to a power supply potential other than the ground potential.

28. The logic device of claim 19 wherein the second power supply conductive region is coupled to a ground potential and the first power supply conductive region is coupled to a power supply potential other than the ground potential.

29. The logic device of claim 19 wherein the second current electrode of the first vertical transistor is connected to the first current electrode of the second vertical transistor to form an output node wherein the output node is coupled to a conductive interconnect layer.

30. The logic device of claim 19 wherein the first current electrode of the second vertical transistor is coupled to the second current electrode of the first vertical transistor through a channel region of an interconnect transistor.

31. The logic device of claim 19 wherein a third transistor is coupled to the second transistor.

32. The logic device of claim 19 wherein the first and second transistors are coupled to form a logic device selected from a group consisting of:

a CMOS NAND gate, a PMOS NAND gate, and an NMOS NAND gate.

33. The logic device of claim 19 wherein the first and second transistors are coupled to form a logic device selected from a group consisting of:

a CMOS NOR gate, a PMOS NOR gate, and an NMOS NOR gate.

25. The logic device of claim wherein 19 the first and second current electrodes of the first vertical transistor is of a conductivity type and the first and second current electrodes of the second vertical transistor is of the same conductivity type as the first and second current electrodes of the first vertical transistor.

34. A logic device comprising:

a first vertical transistor having a first current electrode, a second current electrode overlying the first current electrode, and a control electrode which controls a current flow between the first current electrode and the second current electrode; and

a second vertical transistor overlying the first vertical transistor and having a first current electrode coupled to the second current electrode of the first vertical transistor, a second current electrode overlying the first current electrode of the second vertical transistor, and a control electrode which controls a current flow between the first current electrode and the second current electrode;

wherein the first and second vertical transistors are electrically interconnected to form, at least in part, the logic device wherein the logic device performs a predetermined logic function selected from a group consisting of;

AND, OR, NAND, NOR, and XOR.

35. A two-input logic device comprising:

a first vertical transistor having a first current electrode, a second current electrode overlying the first current electrode, and a control electrode which controls a current flow between the first current electrode and the second current electrode;

a second vertical transistor having a first current electrode coupled to the second current electrode of the first vertical transistor to form a first node, a second current electrode overlying the first current electrode of the second vertical transistor, and a control electrode which controls a current flow between the first current electrode and the second current electrode of the second vertical transistor;

a third vertical transistor having a first current electrode coupled to the second current electrode of the second vertical transistor to form a second node, a second current electrode overlying the first current electrode of the third vertical transistor, and a control electrode which controls a current flow between the first current electrode and the second current electrode of the third vertical transistor;

an output conductor coupled to one of either the first node or the second node to provide an output logic signal;

a first power supply conductor coupled to the first current electrode of the first transistor; and

a second power supply conductor coupled to the second current electrode of the third transistor.

36. The device of claim 35 wherein each control electrode of the first, second, and third vertical transistors are coupled to a conductive interconnect carrying one of two logic signals.

37. An integrated circuit comprising:

a first vertical transistor having a first current electrode, a second current electrode overlying the first current electrode, and a control electrode which controls a current flow between the first current electrode and the second current electrode; and

a second vertical transistor having a first current electrode coupled to the second current electrode of the first vertical transistor, a second current electrode overlying the first current electrode of the second vertical transistor, and a control electrode which controls a current flow between the first current electrode and the second current electrode of the second vertical transistor;

wherein the first and second vertical transistors are electrically interconnected to form a logic device wherein the logic device performs a predetermined logic function;

a third vertical transistor having a first current electrode, a second current electrode overlying the first current electrode of the third vertical transistor, and a control electrode which controls a current flow between the first current electrode and the second current electrode of the third vertical transistor, the third vertical transistor being laterally separated from the first vertical transistor; and

a fourth vertical transistor having a first current electrode coupled to the second current electrode of the third vertical transistor, a second current electrode overlying the first current electrode of the fourth vertical transistor, and a control electrode which controls a current flow between the first current electrode and the second current electrode of the fourth vertical transistor;

wherein a conductive interconnection layer is coupled between one of the first current electrode, the second current electrode, and the control electrode of the first transistor and one of the first current electrode, the second current electrode, and the control electrode of the third transistor.

38. A logic device comprising:

a first vertical transistor having a first current electrode, a second current electrode overlying the first current electrode, and a control electrode which controls a current flow between the first current electrode and the second current electrode;

a second vertical transistor overlying the first vertical transistor and having a first current electrode coupled to the second current electrode of the first vertical transistor, a second current electrode overlying the first current electrode of the second vertical transistor, and a control electrode which controls a current flow between the first current electrode and the second current electrode; and

an output conductor coupled to the first vertical transistor wherein a portion of the output conductor overlies a portion of the control electrode of the first transistor;

wherein the first and second vertical transistors are electrically interconnected to form the logic device wherein the logic device performs a predetermined logic function.

39. A logic device comprising:

a substrate having a top surface;

a first vertical transistor having a first current electrode coupled to a first power supply conductive region, a second current electrode overlying the first current electrode, a channel region separating the first current electrode and the second current electrode, a gate dielectric layer having a first side and a second side wherein the first side is abutting the channel region and the second side is abutting at least one gate electrode wherein the gate dielectric layer separates the channel region and the at least one gate electrode; and

a second vertical transistor overlying the first vertical transistor, the second vertical transistor having a first current electrode coupled to the second current electrode of the first vertical transistor, a second current electrode overlying the first current electrode of the second transistor, the second current electrode being coupled to a second power supply conductive region, a channel region separating the first current electrode and the second current electrode, a gate dielectric layer having a first side and a second side wherein the first side is abutting the channel region and the second side is abutting at least one gate electrode wherein the gate dielectric layer separates the channel region and the at least one gate electrode, the second current electrode of the second vertical transistor overlying the top surface of the substrate, the first and second current electrodes of the first vertical transistor is of a conductivity type and the the first and second current electrodes of second vertical transistor is of the same conductivity type as the first and second current electrodes of the first vertical transistor;

an output conductive layer coupled to a location between the first and second transistors, the output conductive layer providing an output signal from the first and second transistors and being isolated by dielectric material and overlying the top surface of the substrate.

40. A logic device comprising:

a substrate having a top surface;

a first vertical transistor having a first current electrode coupled to a first power supply conductive region, a second current electrode overlying the first current electrode, a channel region separating the first current electrode and the second current electrode, a gate dielectric layer having a first side and a second side wherein the first side is abutting the channel region and the second side is abutting at least one gate electrode wherein the gate dielectric layer separates the channel region and the at least one gate electrode; and

a second vertical transistor overlying the first vertical transistor, the second vertical transistor having a first current electrode coupled to the second current electrode of the first vertical transistor through a channel region of a third transistor, a second current electrode overlying the first current electrode of the second transistor, the second current electrode being coupled to a second power supply conductive region, a channel region separating the first current electrode and the second current electrode, a gate dielectric layer having a first side and a second side wherein the first side is abutting the channel region and the second side is abutting at least one gate electrode wherein the gate dielectric layer separates the channel region and the at least one gate electrode, the second current electrode of the second vertical transistor overlying the top surface of the substrate;

an output conductive layer coupled to a location between the first and second transistors, the output conductive layer providing an output signal from the first and second transistors and being isolated by dielectric material and overlying the top surface of the substrate.