Wireless audible indications system

• US 5,612,666 A
• Filed: 07/29/1994
• Issued: 03/18/1997
• Est. Priority Date: 07/29/1994
• Status: Expired due to Fees

• Current Assignee: Lamson & Sessions Company (ABB Limited)
• Original Assignee: Dimango Products Corp (ABB Limited)
• Inventors: Xydis, Thomas G.
• Primary Examiner(s): Hofsass, Jeffery
• Assistant Examiner(s): POPE, DARYL C
• Application Number:
  US08/282,709
• Time in Patent Office: 963 Days
• Field of Search: 340/539, 340/825.69, 340/825.72, 340/384.7, 340/384.1, 340/384.71, 340/384.72, 340/384.73, 340/692, 341/176, 455/336, 455/339
• US Class Current: 340/384.1
• CPC Class Codes: G08B 3/10 using electric transmission; using electromagnetic transmission

Abstract

A wireless audible indication system comprising a transmitter and a receiver. An embodiment of the transmitter includes a crystal oscillator which produces a signal having a predetermined audio frequency. A duty cycle limiting circuit limits the duty cycle of the oscillator signal to be less than 25%. The limited duty cycle signal is applied to a radio frequency oscillator to produce an amplitude modulated radio frequency signal. An embodiment of the receiver includes a superregenerative detector which provides wide band detection of transmissions about a carrier frequency. A signal processing circuit formed by a cascade of a crystal filter stage, an amplifier/comparator stage, and a detector stage, processes the signal from the superregenerative detector. A sound generator integrated circuit, which generates an audible signal indicative of reception of a transmitted signal, is coupled to the signal processing circuit. Another embodiment of the receiver includes two parallel signal processing paths having different crystal filter stages, which allows use with two different transmitters.

Claims

1. A receiver for use in an audible indication system with a corresponding transmitter which transmits a radio frequency signal, the receiver comprising:

a radio frequency detector which produces a first signal upon receiving the radio frequency signal from the corresponding transmitter;

a signal processing circuit, coupled to the radio frequency detector, which processes the first signal to form a second signal, the signal processing circuit having a series of cascaded stages which includes a filter stage and an amplification stage, wherein the amplification stage includes a first inverter gate having an input and an output, a feedback network coupled between the input and the output of the first inverter gate to produce a fixed voltage level at the output of the first inverter gate, and a second inverter gate having an input biased using the output of the first inverter gate, wherein the output of the second inverter gate provides a processed signal having an AC component based upon an input signal AC coupled to the input of the second inverter gate and a DC component based on the output of the first inverter gate, and wherein the filter stage precedes the amplification stage; and

a sound generator, coupled to the signal processing circuit, which generates an audible indication when the second signal is indicative of reception of the radio frequency signal.

2. The receiver of claim 1 wherein the radio frequency detector includes a superregenerative detector.

3. The receiver of claim 1 wherein the signal processing circuit further includes a low frequency detector coupled to the amplification stage.

4. The receiver of claim 3 wherein the low frequency detector succeeds the amplification stage.

5. The receiver of claim 1 wherein the first inverter gate and the second inverter gate are within a common integrated circuit.

6. The receiver of claim 5 wherein the common integrated circuit is a CMOS device which contains a plurality of MOS field effect transistors.

7. The receiver of claim 1 wherein the feedback network includes a resistor which couples the input and the output of the first inverter gate.

8. The receiver of claim 7 wherein an input of the amplification stage is coupled to the input of the second inverter gate and an output of the amplification stage is coupled to the output of the second inverter gate.

9. The receiver of claim 1 further comprising a voltage divider which divides the output of the first inverter gate for application to the input of the second inverter gate.

10. The receiver of claim 1 wherein the output of the first inverter gate has a voltage equal to a switching threshold voltage of the first inverter gate.

11. The receiver of claim 1 wherein the sound generator includes a music generator integrated circuit.

12. The receiver of claim 11 further comprising a switch coupled to the sound generator, wherein the audible indication is selectable based upon a positioning of the switch.

13. A receiver for use in a doorbell system with a corresponding transmitter which transmits a radio frequency signal, the receiver comprising:

a superregenerative detector which produces a first signal upon receiving the radio frequency signal from the corresponding transmitter;

a signal processing circuit, coupled to the superregenerative detector, which processes the first signal to form a second signal, the signal processing circuit having a series of cascaded stages which includes a filter stage, an amplification stage, and a detector stage, wherein the filter stage contains an audio crystal filter, wherein the amplification stage includes a first inverter gate having an input and an output, a resistor coupled between the input and the output of the first inverter gate so that the output is near the switching threshold voltage, and a second inverter gate having an input biased using the output of the first inverter gate, and wherein the first inverter gate and second inverter gate are located on a common CMOS integrated circuit, wherein the output of the second inverter gate provides a processed signal having an AC component based upon an input signal AC coupled to the input of the second inverter gate and a DC component based on the output of the first inverter gate;

a voltage regulator having an output voltage near to the threshold voltage of MOS field effect transistors within the common CMOS integrated circuit, the voltage regulator coupled to the CMOS integrated circuit to provide power thereto; and

a sound generator, coupled to the signal processing circuit, which generates an audible indication when the second signal is indicative of reception of the radio frequency signal.

14. For use in a wireless actuator system, a signal processing circuit comprising:

a first inverter gate having an input and an output;

a feedback network coupled between the input and the output of the first inverter gate to produce a fixed voltage level at the output of the first inverter gate; and

a second inverter gate having an input and an output, wherein the input is biased using the output of the first inverter gate;

wherein the output of the second inverter gate provides a processed signal having an AC component based upon an input signal AC coupled to the input of the second inverter gate and a DC component based on the output of the first inverter gate.

15. The signal processing circuit of claim 14 further comprising a voltage divider which divides the output of the first inverter gate for application to the input of the second inverter gate.

16. The signal processing circuit of claim 14 wherein the signal processing circuit is powered by a power supply, and wherein the output of the first inverter gate has a voltage near to a switching threshold of the first inverter gate.

17. The signal processing circuit of claim 14 further comprising a capacitor which couples the input signal to the input of the second inverter gate.

18. The signal processing circuit of claim 14 wherein the first inverter gate and the second inverter gate are within a common integrated circuit.

19. For use in a wireless actuator system, a signal processing circuit comprising:

a first inverter gate having an input and an output, the first inverter gate having a switching threshold;

a resistor coupled between the input and the output of the first inverter gate so that the output of the first inverter gate has a voltage near to the switching threshold of the first inverter gate;

a second inverter gate having an input and an output;

a voltage divider which divides the output of the first inverter gate for application to the input of the second inverter gate; and

a capacitor which couples an input signal to the input of the second inverter gate;

wherein the first inverter gate and the second inverter gate are within a common CMOS integrated circuit, and wherein the output of the second inverter gate provides a processed signal based upon the input signal.