Digital micro-mirror device with block data loading

• US 5,612,713 A
• Filed: 01/06/1995
• Issued: 03/18/1997
• Est. Priority Date: 01/06/1995
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Townson, William R., Overlauer, Michael J., Conner, James L., Bhuva, Rohit L.
• Primary Examiner(s): Harvey, David E.
• Application Number:
  US08/369,247
• Time in Patent Office: 802 Days
• Field of Search: 345/84, 345/85, 345/103, 345/94-100
• US Class Current: 345/84
• CPC Class Codes: G09G 2300/0814 used for selection purposes, e.g. logical AND for partial update
• CPC Class Codes: G09G 2300/0842 forming a memory circuit, e.g. a dynamic memory with one capacitor
• CPC Class Codes: G09G 2310/027 Details of drivers for data electrodes, the drivers handling digital grey scale data, e.g. use of D/A converters
• CPC Class Codes: G09G 3/2022 using sub-frames
• CPC Class Codes: G09G 3/2085 Special arrangements for addressing the individual elements of the matrix, other than by driving respective rows and columns in combination
• CPC Class Codes: G09G 3/34 by control of light from an independent source
• CPC Class Codes: G09G 3/346 based on modulation of the reflection angle, e.g. micromirrors micromirrors devices per se G02B26/0833

Abstract

A digital micro-mirror device (20) for imaging applications, having an array (21) of mirror elements for forming the image and data loading circuitry (22, 23, 24) for loading data for addressing the mirror elements. The data loading circuitry (22, 23, 24) has a row of shift registers (24), which receive one row of data at a time, which they deliver to latches (23). The latches (23) hold the data on bit-lines, which run down columns of the array (21). The row to be loaded is selected with a row decoder (25). A block load circuit (22), comprised of a shift register (35) and logic gates (33) divides each row of memory cells into blocks (31) and ensures that each block of a row of memory cells is sequentially loaded.

Claims

1. A spatial light modulator (SLM), comprising:

an array of pixel-generating elements, each pixel-generating element being individually addressable with data, said array of pixel-generating elements having an associated array of memory cells for storing said data;

at least one bit-line associated with each column of memory cells for delivering data to said column of memory cells;

a row of shift registers for receiving row data for one row of said array from an external source for delivery to said memory cells;

a row of latches for receiving said row data from said shift registers, and for holding said row data on said bit-lines;

a block load circuit, interposed between said latches and said memory cells, for sequencing the delivery of said row data to a selected row of said memory cells by delivering a write signal to different blocks of said selected row of memory cells, with each block receiving said write signal at a different time; and

a row decoder for delivering a row select signal to said block load circuit for determining which row of said memory cells is said selected row of memory cells.

2. The SLM of claim 1, wherein said spatial light modulator is a digital micro-mirror device, and wherein said pixel-generating elements are mirror elements.

3. The SLM of claim 1, wherein said pixel-generating elements have a one-to-one relationship with said memory cells.

4. The SLM of claim 1, wherein said pixel-generating elements are in groups, with each group in data communication with only one of said memory cells.

5. The SLM of claim 1, wherein said block load circuit has a shift register that sequentially delivers a block load signal to a logic gate at the input of each block.

6. The SLM of claim 1, wherein said block load circuit has a logic gate at the input of each block for receiving said row select signal and said block load signal.

7. The SLM of claim 1, wherein said block load circuit has a shift register that sequentially delivers a block load signal to a logic gate at the input of each block, said logic gate for outputting said write signal based on the states of said row select signal and said block load signal.

8. The SLM of claim 1, wherein said bit-lines comprise a bit-line and a complement bit-line to each said memory cell.

9. The SLM of claim 1, wherein said bit-lines comprise a single bit-line to each said memory cell.

10. A method of loading data to a spatial light modulator having individually addressable pixel-generating elements, comprising the steps of:

receiving a row of data into a row of shift registers;

delivering said row of data to a row of latches;

holding said row of data on bit-lines that run down columns of said pixel-generating elements;

selecting a row of pixel-generating elements to be addressed with said row of data by means of a row select signal;

sequentially loading memory cells of said row of pixel-generating elements in blocks of said memory cells; and

repeating the above steps for different rows of data to be loaded to said spatial light modulator.

11. The method of claim 10, wherein said selecting step is performed with a row decoder.

12. The method of claim 10, wherein said loading step is performed with a logic gate at the input of each said block that receives said row select signal.

13. The method of claim 10, wherein said loading step is performed with a logic gate at the input of each said block that receives said row select signal and a load signal that shifts from block to block of the selected row of pixel-generating elements.

14. The method of claim 13, wherein said load signal is generated with a shift register.

15. The method of claim 13, wherein said load signal is generated with a D flip-flop shift register.

16. A digital micro-mirror device (DMD), comprising:

an array of mirror elements, each mirror element being individually addressable with data, said array of mirror elements having an associated array of memory cells for storing said data;

at least one bit-line associated with each column of memory cells for delivering data to said column of memory cells;

a row of shift registers for receiving row data for one row of said array from an external source for delivery to said memory cells;

a row of latches for receiving said row data from said shift registers, and for holding said row data on said bit-lines;

a block load circuit, interposed between said latches and said memory cells, for sequencing the delivery of said row data to a selected row of said memory cells by delivering a write signal to different blocks of said selected row of memory cells, with each block receiving said write signal at a different time; and

a row decoder for delivering a row select signal to said block load circuit for determining which row of said memory cells is said selected row of memory cells.