Hardware logic emulation system with memory capability

• US 5,612,891 A
• Filed: 06/06/1995
• Issued: 03/18/1997
• Est. Priority Date: 10/05/1988
• Status: Expired due to Term

• Current Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Original Assignee: Quickturn Design Systems Incorporated (Cadence Group)
• Inventors: Butts, Michael R., Batcheller, Jon A.
• Primary Examiner(s): Trans, Vincent N.
• Application Number:
  US08/470,751
• Time in Patent Office: 651 Days
• Field of Search: 364/488, 364/489, 364/490, 364/491, 364/578, 395/500, 326/39, 326/41, 340/825.83
• US Class Current: 326/38
• CPC Class Codes: G06F 30/331 with hardware acceleration, e.g. by using field programmable gate array [FPGA] or emulation
• CPC Class Codes: G06F 30/34 for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
• CPC Class Codes: G06F 30/347 Physical level, e.g. placement or routing
• CPC Class Codes: G06F 30/39 Circuit design at the physical level physical level design for reconfigurable circuits G06F30/347

Abstract

A plurality of electronically reconfigurable gate array (ERCGA) logic chips are interconnected via a reconfigurable interconnect, and electronic representations of large digital networks are converted to take temporary actual operating hardware form on the interconnected chips. The reconfigurable interconnect permits the digital network realized on the interconnected chips to be changed at will, making the system well suited for a variety of purposes including simulation, prototyping, execution and computing. The reconfigurable interconnect may comprise a partial crossbar that is formed of ERCGA chips dedicated to interconnection functions, wherein each such interconnect ERCGA is connected to at least one, but not all of the pins of a plurality of the logic chips. Other reconfigurable interconnect topologies are also detailed.

Claims

1. An electrically reconfigurable hardware emulation apparatus which can be configured with a circuit design in response to the input of circuit information, the circuit design including memory resources, said electrically reconfigurable hardware emulation apparatus comprising:

a plurality of electrically reconfigurable devices, at least some of said electrically reconfigurable devices containing reprogrammable functional logic elements and input/output terminals capable of being connected to at least some of said functional logic elements,

at least one other of said electrically reconfigurable devices containing reprogrammable electrical conductors which are used to reconfigurably interconnect selected input/output terminals of selected electrically reconfigurable devices containing functional logic elements such that selected functional logic elements in one of said selected electrically reconfigurable devices containing functional logic elements can be electrically coupled to selected functional logic elements in another of said selected electrically reconfigurable devices containing functional logic elements; and

at least one memory device electrically coupled to selected input/output terminals of at least one predetermined electrically reconfigurable device in said plurality of electrically reconfigurable devices.

2. An electrically reconfigurable hardware emulation apparatus as set forth in claim 1, further comprising electrical conductors for carrying address signals, data signals and control signals between said memory device and said predetermined electrically reconfigurable device.

3. An electrically reconfigurable hardware emulation apparatus as set forth in claim 1, wherein said plurality of electrically reconfigurable devices are arranged on a first support structure and said memory device is mounted on a second support structure.

4. An electrically reconfigurable hardware emulation apparatus as set forth in claim 1, wherein said plurality of electrically reconfigurable devices comprise field programmable gate arrays.

5. An electrically reconfigurable hardware emulation apparatus as set forth in claim 1, further comprising a plurality of fixed electrical conductors connected between said electrically reconfigurable devices containing functional logic elements and said electrically reconfigurable devices containing reprogrammable electrical conductors.

6. An electrically reconfigurable hardware emulation system comprising:

a plurality of electrically reconfigurable devices, at least some of said electrically reconfigurable devices containing reprogrammable functional logic elements and input/output terminals capable of being connected to at least some of said functional logic elements, and at least one other of said electrically reconfigurable devices containing reprogrammable electrical conductors which are used to reconfigurably interconnect selected input/output terminals of selected electrically reconfigurable devices containing functional logic elements such that selected functional logic elements in one of said selected electrically reconfigurable devices containing functional logic elements can be electrically coupled to selected functional logic elements in another of said selected electrically reconfigurable devices containing functional logic elements;

at least one memory device electrically coupled to selected input/output terminals of at least one predetermined electrically reconfigurable device in said plurality of electrically reconfigurable devices; and

a computer programmed to receive design input data containing circuit information including information about circuit memory capability and to partition and route said circuit information, said computer also being programmed to generate configuration information which is transmitted to said electrically reconfigurable devices and used for programming said electrically reconfigurable devices to emulate a circuit design with memory capability.

7. An electrically reconfigurable hardware emulation system as set forth in claim 6, wherein said computer comprises a partitioning computer program which partitions said circuit information into portions, a routing computer program which assigns connections between said portions, and a configuration computer program which generates configuration information after said circuit information has been partitioned and routed, said configuration information serving to program logic functions and interconnections associated with said circuit information into said electrically reconfigurable devices.

8. An electrically reconfigurable hardware emulation apparatus which can be configured with a circuit design in response to the input of circuit information, the circuit design including memory resources, said electrically reconfigurable hardware emulation apparatus comprising:

a first group of field programmable gate arrays, each of said first group of field programmable gate arrays including reprogrammable functional logic elements and input/output terminals capable of being connected to said functional logic elements;

a second group of field programmable gate arrays, each of said second group of field programmable gate arrays including reprogrammable electrical conductors and input/output terminals which can be reconfigurably interconnected to one another via said reprogrammable electrical conductors;

a group of fixed conductors connected between at least some of said input/output terminals of said first group of field programmable gate arrays and at least some of said input/output terminals of said second group of field programmable gate arrays such that selected ones of said first group of field programmable gate arrays are electrically coupled to selected functional logic elements in selected others of said first group of field programmable gate arrays; and

at least one memory device electrically coupled to selected input/output terminals of at least one field programmable gate array from said first and second groups of field programmable gate arrays.

9. An electrically reconfigurable hardware emulation apparatus as set forth in claim 8, further comprising a computer programmed to receive design input data containing circuit information including information about circuit memory capability and to partition and route said circuit information, said computer also being programmed to generate configuration information which is transmitted to said first and second groups of field programmable gate arrays and used for programming said first and second group of field programmable gate arrays to emulate a circuit design with memory capability.

10. An electrically reconfigurable hardware emulation apparatus as set forth in claim 8, further comprising electrical conductors for carrying address signals, data signals and control signals between said memory device and said field programmable gate array electrically coupled said memory device.