Method and apparatus for compacting integrataed circuits with transistor sizing

• US 5,612,893 A
• Filed: 05/24/1996
• Issued: 03/18/1997
• Est. Priority Date: 12/22/1993
• Status: Expired due to Fees

• Current Assignee: VLSI Technology, Inc. (Koninklijke Philips N.V.)
• Original Assignee: VLSI Technology, Inc. (Koninklijke Philips N.V.)
• Inventors: Hao, Ling-Hui, Edwards, Lawrence B.
• Primary Examiner(s): Teska, Kevin J.
• Assistant Examiner(s): GARBOWSKI, LEIGH M
• Application Number:
  US08/653,476
• Time in Patent Office: 298 Days
• Field of Search: 364/488, 364/489, 364/490, 364/491
• US Class Current: 716/55
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36

Abstract

A computer-aided design method and apparatus for compacting semiconductor circuit layouts to meet a specified set of design rules begins by fracturing a specified circuit layout into a set of trapezoids and storing the resulting cells in a database identifying the boundaries of each cell, and the cell adjacent each boundary. Nonempty cells are identified as being of specific materials, and empty spaces between cells are represented in the database. For each cell boundary, the database also stores data representing the boundary edge'"'"'s end points. Neighboring cells on the same and related layers of the circuit layout share edges in the database. When a point on an edge of a cell is moved, the edge of each neighboring cell that shares that point is also moved. However, the method sizes gate cells of transistors differently from other cells by maintaining the former at predetermined dimensions, with a user-definable override to resize transistors to a percentage of the predetermined dimensions.

Claims

1. A method executed by a computer under the control of a program, said computer including a memory for storing said program, said method comprising the steps of:

receiving input data representing a semiconductor mask pattern for an integrated circuit layout;

invoking a set of compaction design rules to be satisfied by said semiconductor mask pattern;

identifying transistor gate cells within said semiconductor mask pattern;

compacting said semiconductor mask pattern, including individual cells of said semiconductor mask pattern, except said transistor gate cells, in accordance with said set of compaction design rules.

2. The method of claim 1 further comprising the step of:

applying a transistor scaling value to said transistor gate cells of said semiconductor mask pattern so as to maintain predetermined minimum dimensions for said transistor gate cells.

3. A computer readable memory that can be used to direct a computer to function in a specified manner, comprising:

a first set of executable instructions including a set of compaction design rules to be satisfied by a semiconductor mask pattern of an integrated circuit layout;

a second set of executable instructions to identify transistor gate cells within said semiconductor mask pattern;

a third set of executable instructions to compact said semiconductor mask pattern, including individual cells of said semiconductor mask pattern, except said transistor gate cells, in accordance with said set of compaction design rules.

4. The computer readable memory of claim 3 further comprising

a fourth set of executable instructions to apply a transistor scaling value to said transistor gate cells of said semiconductor mask pattern so as to maintain predetermined minimum dimensions for said transistor gate cells.