Multi-media serial line switching adapter for parallel networks and heterogeneous and homologous computer systems

• US 5,612,953 A
• Filed: 10/18/1995
• Issued: 03/18/1997
• Est. Priority Date: 02/22/1991
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Olnowich, Howard T.
• Primary Examiner(s): Olms, Douglas W.
• Assistant Examiner(s): Patel, Ajit
• Application Number:
  US08/544,625
• Time in Patent Office: 517 Days
• Field of Search: 370/60.16, 370/60.1, 370/94.1, 370/94.2, 370/94.3, 370/58.1-58.3, 340/895.79, 340/895.8
• US Class Current: 370/367
• CPC Class Codes: G06F 15/17375 One dimensional, e.g. linear array, ring
• CPC Class Codes: H04L 1/0057 Block codes H04L1/0061, H04L1/0064 take precedence
• CPC Class Codes: H04L 12/1881 with schedule organisation, e.g. priority, sequence management
• CPC Class Codes: H04L 2012/5627 Fault tolerance and recovery
• CPC Class Codes: H04L 49/153 ATM switching fabrics having parallel switch planes
• CPC Class Codes: H04L 49/256 Routing or path finding in ATM switching fabrics
• CPC Class Codes: H04L 49/3081 ATM peripheral units, e.g. policing, insertion or extraction
• CPC Class Codes: H04L 7/0338 the correction of the phase error being performed by a feed forward loop
• CPC Class Codes: H04L 7/044 using a single bit, e.g. start stop bit
• CPC Class Codes: H04Q 11/0066 Provisions for optical burst or packet networks

Abstract

A generic network device for performing parallel or serial communications amongst multiple nodes over switching networks. An aspect is the adaptation of standard or proprietary serial interfaces using optical or electrical transmission to interface to the parallel switch. Converted serial data is routed to the selected destination through the parallel switch network. At the destination the data is converted back to a serial optical or electrical interface/protocol. Any number of different serial protocols can interface with the same parallel switch network allowing every node of the parallel system to send and receive messages in its native protocol. The switch enables generic networks forming a computer system with heterogeneous or homologous nodes.

Claims

1. A multi-stage bufferless and clockless switch network comprising:

a plurality of bufferless and clockless switch apparatuses cascaded into a plurality of stages, said switch apparatuses each including a plurality of switch inputs and a plurality of switch outputs, of the switch outputs included in each of said switch apparatuses each coupled to a different one of the switch apparatuses via a switch input of said different one of the switch apparatuses, switch outputs of last stage switch apparatuses each comprising a network output port and switch inputs of first stage switch apparatuses each comprising a network input port; and

said network output ports each coupled to a network input port through one of a plurality of nodes, each of said nodes comprising;

a processor operating under a native protocol, said native protocol different from an operating protocol of at least one other of the nodes;

means for receiving a data message from a coupled network output port; and

means for sending a data message to a coupled network input port, said data message to a coupled network input port including a path connection request;

said switch apparatuses each further including;

connection means for establishing a point-to-point communication path between any one of the network input ports and any one of the network output ports in response to said connection request received at said any one of the network input ports, said point-to-point communication path for transmitting a data message received at said any one of the network input ports to said any one of the network output ports;

multicast means for establishing a multicast communication path between said any one of the network input ports and any portion of the network output ports in response to said connection request received at said any one of the network input ports, said multicast communication path for transmitting the data message received at said any one of the network input ports simultaneously to said any portion of the network output ports;

broadcast means for establishing a broadcast communication path between said any one of the network input ports and all of the network output ports in response to said connection request received at said any one of the network input ports, said broadcast communication path for transmitting the data message received at said any one of the network input ports simultaneously to said all of the network output ports; and

asynchronous connection means for establishing asynchronously, in response to a plurality of path connection requests received separately or simultaneously at a plurality of network input ports, a plurality of concurrently active;

point-to-point communication paths,

multicast communication paths, and

point-to-point and multicast communications paths in combination,

said plurality of concurrently active point-to-point communication paths, multicast communication paths, and point-to-point and multicast communications paths in combination for transmitting concurrently a plurality of data messages received separately or simultaneously at said plurality Of the network input ports to a plurality of the network output ports.

2. The multi-stage bufferless and clockless switch network according to claim 1, wherein at least two processors each from separate nodes each comprise a parallel processing program for enabling processing in parallel, by said at least two processors, portions of an application program.

3. The multi-stage bufferless and clockless switch network according to claim 1, further comprising means for establishing any communication path in two data transmission cycles for each stage of the network traversed by said any communication path.

4. The multi-stage bufferless and clockless switch network according to claim 1, wherein the means for sending a data message to a coupled network input port includes a software interface driver for converting serial data to parallel data.

5. The multi-stage bufferless and clockless switch network according to claim 4, wherein the means for receiving a data message from a coupled network output port includes a software interface driver for converting parallel data to serial data.

6. The multi-stage bufferless and clockless switch network according to claim 5, wherein the means for sending and the means for receiving a data message include, respectively, means for sending and means for recognizing bit patterns denoting a start and an end of a data message.

7. The multi-stage bufferless and clockless switch network according to claim 2, wherein said application program includes a subroutine for transferring portions of the application program between said at least two processors.

8. The multi-stage bufferless and clockless switch network according to claim 2, wherein said application program includes a first subroutine for executing on a first one of said at least two processors and a second subroutine for executing on a second one of said at least two processors.

9. The multi-stage bufferless and clockless switch network according to claim 1, wherein each of the nodes further comprise a parallel processing program for enabling processing concurrently and in parallel, by all of the nodes, portions of an application program.