Hybrid pattern self-testing of integrated circuits
First Claim
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1. A digital test signal generation circuit comprising:
- means for generating a pseudo-random sequence of binary digits;
weight storage means for storing a sequence of pairs of weight bits, each pair including a first weight bit and a second weight bit;
conjunctive circuit means for receiving, as a first input, a single bit from said generating means and, as a second input, said first weight bit from said weight storage means and for operating on said first and second inputs in non-inverted form to produce output signals; and
disjunctive circuit means for receiving, as a first input, said output signals from said conjunctive circuit means and, as a second input, said second weight bit from said weight storage means, the output signal from said disjunctive circuit means being said test signal.
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Abstract
A hybrid random pattern self-test approach is employed in an on-chip fashion to provide desired test signals to circuits on the chip. A simplified weighting circuit is shown to be effective even when only a single bit from a linear feedback shift register is employed for random signal generation. The reduction in linear feedback shift register size and associated weighting circuitry enables the apparatus to be much more readily usable in an on-product configuration thus resulting in significant initial and subsequent test circuit advantages.
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Citations
13 Claims
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1. A digital test signal generation circuit comprising:
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means for generating a pseudo-random sequence of binary digits; weight storage means for storing a sequence of pairs of weight bits, each pair including a first weight bit and a second weight bit; conjunctive circuit means for receiving, as a first input, a single bit from said generating means and, as a second input, said first weight bit from said weight storage means and for operating on said first and second inputs in non-inverted form to produce output signals; and disjunctive circuit means for receiving, as a first input, said output signals from said conjunctive circuit means and, as a second input, said second weight bit from said weight storage means, the output signal from said disjunctive circuit means being said test signal. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A digital test signal generation circuit comprising:
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means for generating a pseudo-random sequence of binary digits; weighting means including a first means for receiving a single bit in non-inverted form from said pseudo-random sequence of binary digits and for receiving a first weighting signal supplied to said first means, said weighting means also including a second means for receiving the output of said first means and a second weighting signal for producing a weighted output sequence in which output binary digit distribution is altered; and weight storage means for storing a sequence of weighting signals for transmittal to said weighting means. - View Dependent Claims (9, 10, 11, 12, 13)
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Specification