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Hybrid pattern self-testing of integrated circuits

  • US 5,612,963 A
  • Filed: 06/07/1995
  • Issued: 03/18/1997
  • Est. Priority Date: 08/23/1991
  • Status: Expired due to Term
First Claim
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1. A digital test signal generation circuit comprising:

  • means for generating a pseudo-random sequence of binary digits;

    weight storage means for storing a sequence of pairs of weight bits, each pair including a first weight bit and a second weight bit;

    conjunctive circuit means for receiving, as a first input, a single bit from said generating means and, as a second input, said first weight bit from said weight storage means and for operating on said first and second inputs in non-inverted form to produce output signals; and

    disjunctive circuit means for receiving, as a first input, said output signals from said conjunctive circuit means and, as a second input, said second weight bit from said weight storage means, the output signal from said disjunctive circuit means being said test signal.

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