Hybrid pattern self-testing of integrated circuits

• US 5,612,963 A
• Filed: 06/07/1995
• Issued: 03/18/1997
• Est. Priority Date: 08/23/1991
• Status: Expired due to Term

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Waicukauski, John A., Koenemann, Bernd K. F., Wagner, Kenneth D.
• Primary Examiner(s): Nguyen, Hoa T.
• Application Number:
  US08/486,100
• Time in Patent Office: 650 Days
• Field of Search: 371/27, 371/22.3, 371/22.4, 371/25.1, 395/183.01, 364/717
• US Class Current: 714/739
• CPC Class Codes: G01R 31/31813 Test pattern generators
• CPC Class Codes: G01R 31/318385 Random or pseudo-random test pattern
• CPC Class Codes: G06F 11/27 Built-in tests

Abstract

A hybrid random pattern self-test approach is employed in an on-chip fashion to provide desired test signals to circuits on the chip. A simplified weighting circuit is shown to be effective even when only a single bit from a linear feedback shift register is employed for random signal generation. The reduction in linear feedback shift register size and associated weighting circuitry enables the apparatus to be much more readily usable in an on-product configuration thus resulting in significant initial and subsequent test circuit advantages.

Claims

1. A digital test signal generation circuit comprising:

means for generating a pseudo-random sequence of binary digits;

weight storage means for storing a sequence of pairs of weight bits, each pair including a first weight bit and a second weight bit;

conjunctive circuit means for receiving, as a first input, a single bit from said generating means and, as a second input, said first weight bit from said weight storage means and for operating on said first and second inputs in non-inverted form to produce output signals; and

disjunctive circuit means for receiving, as a first input, said output signals from said conjunctive circuit means and, as a second input, said second weight bit from said weight storage means, the output signal from said disjunctive circuit means being said test signal.

2. The circuit of claim 1 in which said generating means comprises a linear feedback shift register.

3. The circuit of claim 1 in which said weight storage means comprises a random access memory.

4. The circuit of claim 1 in which said weight storage means comprises a read only memory.

5. The circuit of claim 1 disposed on a circuit chip device the circuits of which receive said weighted output sequence for testing.

6. The circuit of claim 1 in which said conjunctive circuit means is an AND-gate.

7. The circuit of claim 1 in which said disjunctive circuit means is an OR-gate.

8. A digital test signal generation circuit comprising:

means for generating a pseudo-random sequence of binary digits;

weighting means including a first means for receiving a single bit in non-inverted form from said pseudo-random sequence of binary digits and for receiving a first weighting signal supplied to said first means, said weighting means also including a second means for receiving the output of said first means and a second weighting signal for producing a weighted output sequence in which output binary digit distribution is altered; and

weight storage means for storing a sequence of weighting signals for transmittal to said weighting means.

9. The circuit of claim 8 in which said generating means comprises a linear feedback shift register.

10. The circuit of claim 8 in which said weight storage means comprises a random access memory.

11. The circuit of claim 8 in which said weight storage means comprises a read only memory.

12. The circuit of claim 8 in which said weighting means comprises:

an AND gate, as said first means, receiving a single bit from said generating means; and

an OR gate, as said second means, which receives the output signal from said AND gate, said AND gate and said OR gate also each receiving a single bit input from said weight storage means.

13. The circuit of claim 8 disposed on a circuit chip device having circuits thereon which circuits receive said weighted output sequence for testing.