Method for transferring data between processors on a network by establishing an address space for each processor in each other processor's

• US 5,613,068 A
• Filed: 06/17/1994
• Issued: 03/18/1997
• Est. Priority Date: 06/17/1994
• Status: Expired due to Term

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Gregg, Thomas A., Ferraiolo, Frank D., Halma, Marten J., Murray, Robert E., Hillock, Thomas H., Capowski, Robert S.
• Primary Examiner(s): Pan, Daniel H.
• Application Number:
  US08/262,081
• Time in Patent Office: 1,005 Days
• Field of Search: 395/200.12, 395/200.13, 395/800, 395/200.08, 395/435, 395/145, 395/308, 395/700, 395/309, 395/431, 395/600, 395/200.07, 364/DIG. 1, 364/DIG. 2, 364/409, 364/408, 370/60, 370/61.1, 370/79, 370/94.1, 340/825.02, 340/825.44
• US Class Current: 709/216
• CPC Class Codes: G06F 15/17 using an input/output type connection, e.g. channel, I/O port
• CPC Class Codes: G06F 15/17375 One dimensional, e.g. linear array, ring

Abstract

A multi-system interconnect facility in which each central processor complex in the system has an assigned storage space for each other central processor complex in the system for use in communicating with each other central processor complex. The allegiance or association of systems to particular storage spaces is established when each system is initialized and enables a simple interface between user program(s) and message passing hardware consisting primarily of instructions for moving control and data blocks between the program addressable space and the hardware addressable space.

Claims

1. A method for transferring data between central processor complexes that are interconnected in a network where each central processor complex comprises a processor, a main memory, and a port for sending and receiving data, said method including the steps of:

partitioning said main memory of each central processor complex into a program system area and a hardware system area;

assigning a system address space in said hardware system area of each central processor complex for each other central processor complex connected via said network;

establishing an address table link for each central processor complex linking an address in said system address space assigned in said assigning step to a central processor complex;

assembling data to be transmitted from one central processor complex to another central processor complex with an address to store said data in said hardware system area in said another central processor complex assigned to said one central processor complex; and

transmitting said data from said one central processor complex to said another central processor complex.

2. A method as in claim 1 wherein said program system area is addressable by said system operating program, and said hardware system area is not addressable by said system operating program.

3. A method as in claim 1 wherein said data is assembled into packets.

4. A method as in claim 1 wherein said another central processor complex stores said data in its said main memory assigned to said one central processor complex and transmits an acknowledge message to said one central processor complex.

5. A method as in claim 2 wherein said another central processor complex stores said data in its said hardware system area assigned to said one central processor complex and transmits an acknowledge message to said one central processor complex.

6. A method for transferring data between central processor complexes that are interconnected in a network where each central processor complex comprises a processor, a main memory, and a port for sending and receiving data, said method including the steps of:

partitioning said main memory of each central processor complex into a program system area and a hardware system area;

assigning a system address space in said hardware system area of each central processor complex for each other central processor complex connected via said network;

establishing an address table link for each central processor complex linking an address in said system address space assigned in said assigning step to a central processor complex;

assembling data to be transmitted from one central processor complex to another central processor complex with an address to store said data in said hardware system area in said another central processor complex assigned to said one central processor complex; and

transmitting said data from said one central processor complex to said another central processor complex.

7. A method as in claim 6 wherein said data is assembled into packets.

8. A method as in claim 6 wherein said another central processor complex stores said data in its said main memory assigned to said one central processor complex and transmits an acknowledge message to said one central processor complex.

9. A method as in claim 6 wherein said network includes a data switch that selectively interconnects each central processor complex in the network with each other central processor in the network, and said transmitting step includes the further step of transmitting said data via said data switch with said data switch coupling data from said central processor complex addressed to said another central processor complex only in response to an acknowledge response from said another central processor complex.

10. A method as in claim 9 wherein said data is assembled into packets.