Method and apparatus for providing remote memory access in a distributed memory multiprocessor system

• US 5,613,071 A
• Filed: 07/14/1995
• Issued: 03/18/1997
• Est. Priority Date: 07/14/1995
• Status: Expired due to Term

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Kapur, Suvansh K., Bonasera, Joseph, Borkar, Nitin Y., Rankin, Linda J., Manseau, Daniel A., Ernst, Linda C., Verhoorn, Frank
• Primary Examiner(s): Coleman, Eric
• Application Number:
  US08/502,071
• Time in Patent Office: 613 Days
• Field of Search: 395/800, 395/412, 395/421.1, 395/421.11, 395/200.16, 395/200.2, 395/410
• US Class Current: 1/1
• CPC Class Codes: G06F 12/0284 Multiple user address space allocation, e.g. using different base addresses interprocessor communication G06F15/163
• CPC Class Codes: G06F 15/17381 Two dimensional, e.g. mesh, torus

Abstract

A massively parallel data processing system is disclosed. This data processing system includes a plurality of nodes, with each node having at least one processor, a memory for storing data, a processor bus that couples the processor to the memory, and a remote memory access controller coupled to the processor bus. The remote memory access controller detects and queues processor requests for remote memory, processes and packages the processor requests into request packets, forwards the request packets to the network through a router that corresponds to that node, receives and queues request packets received from the network, recovers the memory request from the request packet, manipulates local memory in accordance with the request, generates an appropriate response packet acceptable to the network and forwards the response packet to the requesting node.

Claims

1. In a massively parallel data processing system having a plurality of nodes, with the nodes connected together through a network, wherein each node includes a processor;

a memory for storing data;

a processor bus coupling the processor to the memory for facilitating communication and data transfer to and from the processor and the memory; and

a remote memory access controller, coupled to the bus, for detecting and processing remote memory access requests, said remote memory access controller comprising;

(a) a remote memory access request mapping module coupled to the processor bus for detecting a remote memory access request;

(b) a processor bus interface coupled to the processor bus and the remote memory access request mapping module for providing an interface between the processor and the remote memory access controller;

(c) a packet generator coupled to the processor bus interface, said processor bus interface receiving a remote memory request, accessing a route table for network route information, and generating a request packet having said network route information, said request packet suitable for transmission on the network;

(d) a packet decoder coupled to the processor bus interface for decoding response packets and request packets into a corresponding response and request;

(e) a bus master module coupled to the packet decoder and to the packet generator, for implementing a remote memory access protocol; and

(f) a network protocol interface coupled to the network, said network protocol interface having at least two lanes, said network protocol interface receiving request packets from the network and sending response packets to the network and detecting network errors in the response and request packets, said network protocol interface adapted to handle multiple outstanding requests and responses.

2. The remote memory access controller of claim 1, wherein a bus master module coupled to the packet decoder and to the packet generator for implementing a remote memory access protocol further includes a plurality of registers and a remote memory access state machine.

3. The remote memory access controller of claim 1 further comprising a plurality of buffers coupled to the network protocol interface, the packet generator and the packet decoder for queuing request packets and response packets.

4. The remote memory access controller of claim 1, wherein the bus master module further comprises:

at least one memory fence support register corresponding to each processor, for tracking the number of remote memory accesses outstanding for an application running on the processor;

wherein the register is accessible to a system programmer, and

the register is adapted to support memory fences.

5. The remote memory access controller of claim 1, wherein the bus master module further comprises a plurality of atomic memory support registers, said registers including

a first atomic register holding a base address that represents a start address of an atomic region;

and

a second atomic register holding a limit address that represents an end address of the atomic region;

wherein the first atomic register and the second atomic register are accessible to a system programmer and may be used to support atomic memory operations.

6. The remote memory access controller of claim 1, wherein the bus master module further comprises at least one register accessible to a system programmer for error recording and notification.

7. The remote memory access controller of claim 1, wherein the bus master module further includes at least one register accessible to a system programmer for providing software reset and control in remote memory access transactions.

8. The remote memory access controller of claim 1, wherein the processor bus interface and the bus master module are adapted to handle split transactions on the processor bus.

9. The remote memory access controller of claim 8, wherein the processor bus is compliant to the P6 bus specification.

10. A method of mapping a global address to a corresponding physical address at a remote node comprising the steps of:

a) defining a route table at a local node including a number of entries in local physical memory, said route table pointed to by a route-base register holding a start address of the route table;

wherein a node-field in the global address is an offset for determining the location in the route table from the address in the route-base register;

b) forming a base field in the physical address by an entry identified by the node-field;

c) mapping the address field of the global address directly to the offset field of the physical address; and

d) mapping the entry directly into the base field of the physical address.

11. The method of claim 10, further comprising the step of partitioning the total address space into a global address space and a local address space;

wherein the local memory address space begins at a first predetermined physical address in memory and extends to a second predetermined address in memory;

wherein the global addresses begins at a third predetermined address in the memory and extends to a fourth predetermined address;

wherein the local and global address spaces do not overlap;

wherein at least one local address points to a local physical memory location;

wherein a global address points to a remote physical memory location in a remote node, and the global address may point to a physical memory location in the local node in an atomic memory operation; and

wherein each global address must be mapped into a local address by using a route table in the local node to access a physical memory on a remote node.

12. The method of claim 11 further comprising the step of defining an atomic address space beginning at a fifth predetermined physical address and extending to a sixth predetermined physical address;

wherein if an address is within the atomic address space, then a read command to this specified address in atomic memory is performed and a clear operation is automatically performed on this memory location.