Method of compressing data for use in performing VLSI mask layout verification

• US 5,613,102 A
• Filed: 10/19/1995
• Issued: 03/18/1997
• Est. Priority Date: 11/30/1993
• Status: Expired due to Term

• Current Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Original Assignee: Lucent Technologies, Inc. (Nokia Corporation)
• Inventors: Chiang, Kuang-Wei, Lo, Chi-Yuan, Su, Shun-Lin, Paik, Doowan
• Primary Examiner(s): Teska, Kevin J.
• Assistant Examiner(s): Mohamed, Ayni
• Application Number:
  US08/545,109
• Time in Patent Office: 516 Days
• Field of Search: 395/375, 395/800, 395/500, 364/490, 364/491
• US Class Current: 716/52
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36

Abstract

A method of compressing data used in integrated circuit (IC) layout verifications includes the steps of identifying each circuit component from each layer of the IC chip; sorting each circuit component in an established order; identifying predetermined parameters for each component; determining the difference in value of the parameters for each pair of components in successive order; and storing the difference values for each pair of components.

Claims

1. A method of compressing data used in IC layout verifications of an IC chip comprising:

a) identifying each circuit component from each layer of the IC chip;

b) applying a range compression transformation to uncompressed data which reduces the value of the data by a predetermined order of magnitude;

c) arranging each circuit component in an established order based on the physical location of the circuit component within the IC chip;

d) identifying predetermined parameters for each component;

e) performing a differential measurement to determine the difference in value of the parameters for a pair of components in successive order, said differential measurement resulting in a compressed data representation of the parameter values for a second component relative to a first component, said first and second components comprising the pair of components, said second component being a component for which the compressed data representation is currently being recorded and the first component being a component for which a compressed data representation has previously been recorded, said compressed data representation representing the minimal amount of information required to retrieve the parameter values for the second component, said data representation containing relational information for the pair of components, said differential measurement acting as a mechanism for compressing the data representing the circuit components;

f) identifying rectangles contained within a given layer of the chip which are substantially identical;

g) encoding common data attributes in a compact form;

h) storing the compressed data representation for the second component; and

i) repeating steps e) and h) for each successive pair of components contained in the IC chip.

2. The method according to claim 1 wherein said predetermined parameters represent geometric data describing each component in the chip.

3. The method according to claim 2 wherein each component is represented by at least one rectangle and said identifying step further comprises:

identifying coordinate data for each component within the chip representing each rectangle.

4. The method according to claim 3 wherein said coordinate data for a given rectangle comprises diagonally opposite coordinate pairs.

5. The method according to claim 1 wherein said predetermined parameters represent parasitic data.

6. The method according to claim 1 wherein said predetermined parameters represent transistor data.

7. The method according to claim 1 further comprising the step of

scaling down each parameter value by a predetermined order of magnitude.