Operation of a radiotelephone in a synchronous extended standby mode for conserving battery power

• US 5,613,235 A
• Filed: 06/29/1995
• Issued: 03/18/1997
• Est. Priority Date: 06/29/1995
• Status: Expired due to Term

• Current Assignee: Nokia Technologies Oy (Nokia Corporation)
• Original Assignee: Nokia Mobile Phones UK Limited (Nokia Corporation)
• Inventors: Kivari, Raimo K., Kontas, Veijo L.
• Primary Examiner(s): Eisenzopf, Reinhard J.
• Assistant Examiner(s): TO, DORIS HA
• Application Number:
  US08/496,688
• Time in Patent Office: 628 Days
• Field of Search: 455/343, 455/38.3, 455/69, 455/70, 455/75, 455/76, 455/165.1, 455/183.1, 455/260, 375/376, 375/373, 331/14, 331/18
• US Class Current: 455/574
• CPC Class Codes: H04B 1/1615 Switching on; Switching off, e.g. remotely battery saving circuits associated with selective call operation H04W52/00; details of power consumption reduction in a PLL, H03L7/0802, H03L7/14, H03L2207/08, H03L2207/18; muting amplifiers by gain control see H03G3/34
• CPC Class Codes: H04W 52/029 reducing the clock frequency of the controller
• CPC Class Codes: Y02D 30/70 in wireless communication networks

Abstract

A method and system for operating a radiotelephone at reduced power provides for a deenergization of a receiver of the radiotelephone wherein the receiver, during periods of activation, receives a sequence of messages of a control channel, each message having a synchronization portion and a data portion which follows the synchronization portion. Included within the radiotelephone is signal processing circuitry synchronized by a synchronization portion of an individual one of the messages to permit a reading of data of the data portion of an individual one of the messages. A digital phase locked lop (DPLL) with phase adjustment capability enables operation of synchronization circuitry and the data reading circuitry. Electronic circuitry within the DPLL provides for inhibiting the phase adjustment function in response to the command of a controller of the radiotelephone subsequent to a reading of data and concurrently with a termination of power to the receiver. The phase adjustment function is enabled upon reactivation of the receiver and operation of the data reading circuitry for reading data of a subsequent message.

Claims

1. A method for operating a radiotelephone at reduced power, the radiotelephone having a receiver for receiving a sequence of messages of a control channel, each message having a synchronization portion and a data portion which follows the synchronization portion, the radiotelephone having signal processing circuitry including synchronization circuitry responsive to the synchronization portion of an individual one of said messages to permit a reading of data of the data portion of an individual one of said messages, said signal processing circuitry including a digital phase locked loop (DPLL) with phase adjustment capability, said radiotelephone including power application circuitry for application and disconnection of electric power to said receiver, wherein power is applied continuously to the DPLL, the method comprising steps of:

synchronizing the DPLL with bits of a portion of an N^th message of said sequence of messages, the DPLL providing a clock signal to enable a reading of data;

reading data of the data portion of said N^th message;

subsequent to said reading step, inhibiting phase adjustment of the DPLL;

operating the power application circuitry for deactivating the receiver;

operating the power application circuitry for activating the receiver at a predetermined time interval prior to occurrence of a selected part

of the data portion of a message subsequent to a first message, said predetermined time interval being limited in duration to the duration of a transient settling time of the receiver upon the activation of the receiver; and

enabling the phase adjustment capability of the DPLL in an interval of time beginning at or prior to the selected part of the data portion of the subsequent message and continuing during the occurrence of the selected part of the data portion of the subsequent message.

2. A method according to claim 1 wherein the signal processing circuitry includes a clock for driving various components of the signal processing circuitry, the clock comprising a first relatively fast oscillator outputting a signal at a first frequency and being powered by said power application circuitry, a relatively slow oscillator outputting a signal at a second frequency lower than said first frequency and being powered by a steady source of power, frequency generation circuitry driven by the slow oscillator for outputting at least a further signal at a third frequency lower than said second frequency, the frequency generation circuitry including a selector for selecting the fast oscillator signal in place of the slow oscillator signal, said method further comprising steps of:

operating said power application circuitry to deactivate said fast frequency oscillator of said clock substantially concurrently with said deactivating of the receiver; and

operating said power application circuitry for activating fast oscillator of said clock prior to said step of enabling the phase adjustment capability of the DPLL.

3. A method according to claim 1 wherein said reading step includes a reading of a data word at an end of the data portion of an (N-1)^th message of said sequence of messages and a reading of a data word at a beginning of the data portion of the Nth message of said sequence of messages followed by a reading of a data word at an end of the data portion of (N+1)^th message of said sequence of messages and a reading of a data word at a beginning of the data portion of the (N+2)^th message of said sequence of messages.

4. A method according to claim 3 wherein there is a period of time between the reading of the data word of the N^th message and the reading of the data word of the (N+1)^th message, said inhibiting step being performed in a beginning portion of said period and said enabling step being performed in an end portion of said period.

5. A system for operating a radiotelephone at reduced power, the radiotelephone comprising:

a receiver for receiving a sequence of messages of a control channel, each message having a synchronization portion and a data portion which follows the synchronization portion;

signal processing circuitry including synchronization circuitry responsive to the synchronization portion of an individual one of said messages to enable a reading of data of the data portion of an individual one of said messages, said signal processing circuitry including a digital phase locked loop (DPLL) with phase adjustment capability, said signal processing circuitry applying electric power to

said DPLL continuously from a steady source of power, said DPLL being synchronized by bits of a portion of an N^th message of said sequence of messages;

power application circuitry for application of electric power to said receiver;

reading means for accomplishing said reading of data, said reading means reading data of at least a selected part of the data portion of said N^th message;

inhibiting means for inhibiting phase adjustment of the DPLL, and controller means for activating said inhibiting means subsequent to a reading of data by said reading means;

wherein said power application circuitry is operative for deactivating the receiver upon a conclusion of a reading of data of said selected part of the data portion of said N^th message;

said power application circuitry is operative for activating the receiver subsequent to said N^th message at a predetermined time interval prior to occurrence of at least a selected part of the data portion of an (N+1)^th message of said sequence of messages, said predetermined time interval being limited in duration to the duration of a transient settling time of the receiver upon an activation of the receiver; and

said controller means disables said inhibiting means for enabling the phase adjustment capability of the DPLL in an interval of time beginning at or prior to and continuing during the occurrence of the selected part of the data portion of the (N+1)^th message.

6. A system according to claim 5 wherein the signal processing circuitry includes a clock for driving various components of the signal processing circuitry, the clock comprising a first relatively fast oscillator outputting a signal at a first frequency and being powered by said power application circuitry, a relatively slow oscillator outputting a signal at a second frequency lower than said first frequency and being powered by a steady source of power, frequency generation circuitry driven by the slow oscillator for outputting at least a further signal at a third frequency lower than said second frequency, the frequency generation circuitry including a selector for selecting the fast oscillator signal in place of the slow oscillator signal;

wherein said power application circuitry is operative to deactivate said fast oscillator of said clock substantially concurrently with said deactivating of the receiver; and

said power application circuitry is operative for activating said fast oscillator of said clock prior to an enabling of the phase adjustment capability of said DPLL.

7. A system according to claim 5 wherein said reading means is responsive to said controller means to accomplish a reading of a data word at an end of the data portion of an (N-1)^th message of said sequence of messages and a reading of a data word at a beginning of the data portion of the Nth message of said sequence of messages followed by a reading of a data word at an end of the data portion of (N+1)^th message of said sequence of messages and a reading of a data word at a beginning of the data portion of the (N+2)^th message of said sequence of messages.

8. A system according to claim 7 wherein there is a period of time between the reading of the data word of the N^th message and the reading of the data word of the (N+1)^th message, said controller means operating said inhibiting means to inhibit the phase adjustment in a beginning portion of said period and to enable the phase adjustment in an end portion of said period.

9. A system according to claim 5 wherein said DPLL includes phase adjustment means and a phase detector, said inhibiting means comprising an electronic gate interconnecting said phase detector with an input terminal of said phase adjustment means, and wherein said electronic gate is responsive to a command of said controller means for terminating a communication of signals from said phase detector to said phase adjustment means.

10. A system according to claim 5 further comprising timing means responsive to an output reference signal of said DPLL for operating said reading means;

wherein

said reference signal of said DPLL is maintained during periods of deenergization of said receiver for operation of said timing means, said inhibiting of said DPLL accomplishing a freezing of output phase of said reference signal during the periods of deenergization of said receiver.

11. A system according to claim 10 wherein said timing means is operative to count clock pulses of the reference signal outputted by said DPLL during periods of inhibition of phase adjustment by said DPLL and during periods of phase adjustment by said DPLL.

12. A system according to claim 11 wherein said DPLL comprises phase adjustment means operative in response to an enabling signal, and said phase adjustment is inhibited by termination of said enabling signal.

13. A system according to claim 11 wherein said DPLL comprises a counter operative to count clock signal pulses outputted by said clock in response to a presence of data at an input terminal of said counter, and said phase adjustment is inhibited by termination of the presence of said data.

14. A system according to claim 11 wherein said DPLL comprises a counter operative to count clock signal pulses outputted by said clock in response to an enabling signal, and said phase adjustment is inhibited by termination of said enabling signal.

15. A system according to claim 11 wherein said reading means is responsive to said controller means to accomplish a reading of a data word at an end of the data portion of an (N-1)^th message of said sequence of messages and a reading of a data word at a beginning of the data portion of the Nth message of said sequence of messages followed by a reading of a data word at an end of the data portion of (N+1)^th message of said sequence of messages and a reading of a data word at a beginning of the data portion of the (N+2)^th message of said sequence of messages;

and

there is a period of time between the reading of the data word of the N^th message and the reading of the data word of the (N+1)^th message, said controller means operating said inhibiting means to inhibit the phase adjustment in a beginning portion of said period and to enable the phase adjustment in an end portion of said period.

16. A system according to claim 5 wherein the signal processing circuitry includes a clock for driving various components of the signal processing circuitry, the clock comprising a first relatively fast oscillator outputting a signal at a first frequency and being powered by said power application circuitry, a relatively slow oscillator outputting a signal at a second frequency lower than said first frequency and being powered by a steady source of power, frequency generation circuitry driven by the slow oscillator for outputting at least a further signal at a third frequency lower than said second frequency, the frequency generation circuitry including a selector for selecting the fast oscillator signal in place of the slow oscillator signal;

and

said fast oscillator is energized by said power application circuitry, and is selected by said selector for driving said frequency generation circuitry concurrently with operation of said DPLL for adjustment of phase of the reference signal outputted by said DPLL to a timing means.

17. A system according to claim 16 wherein said fast oscillator is deenergized by said power application circuitry, and said slow oscillator is selected by said selector for driving said frequency generation circuitry concurrently with inhibition of the phase adjustment of said DPLL, thereby maintaining accurate timing of said timing means during the periods of deenergization of said receiver and without sync detection for each frame of data.

18. A method for operating a radiotelephone at reduced power, the radiotelephone having a receiver for receiving a sequence of messages of a control channel, each message having a synchronization portion and a data portion which follows the synchronization portion, the data portion comprising a plurality of data channels each of which has a succession of repeated data segments, the radiotelephone having signal processing circuitry including synchronization circuitry responsive to the synchronization portion of an individual one of said messages to permit a reading of data of the data portion of an individual one of said messages, said signal processing circuitry including a digital phase locked loop (DPLL) with phase adjustment capability, said radiotelephone including power application circuitry for application and disconnection of electric power to said receiver, wherein power is applied continuously to the DPLL, the method comprising steps of:

synchronizing the DPLL with a bit stream of a selected data segment of said data segments of an N^th message of said sequence of messages, the DPLL providing a clock signal to enable a reading of data;

reading data of the data segment of said N^th message;

subsequent to said reading step, inhibiting phase adjustment of the DPLL;

operating the power application circuitry for deactivating the receiver;

operating the power application circuitry for activating the receiver at a predetermined time interval prior to occurrence of the selected data segment of the (N+1)^th message of said sequence of messages, said predetermined time interval being limited in duration to the duration of a transient settling time of the receiver upon the activation of the receiver; and

enabling the phase adjustment capability of the DPLL in an interval of time beginning at or prior to the selected data segment of the (N+1)^th message of said sequence of messages and continuing during the occurrence of the selected data segment of said (N+1)^th message.

19. A method according to claim 18 wherein the signal processing circuitry includes a clock for driving various components of the signal processing circuitry, the clock comprising a first relatively fast oscillator outputting a signal at a first frequency and being powered by said power application circuitry, a relatively slow oscillator outputting a signal at a second frequency lower than said first frequency and being powered by a steady source of power, frequency generation circuitry driven by the slow oscillator for outputting at least a further signal at a third frequency lower than said second frequency, the frequency generation circuitry including a selector for selecting the fast oscillator signal in place of the slow oscillator signal, said method further comprising steps of:

operating said power application circuitry to deactivate said fast frequency oscillator of said clock substantially concurrently with said deactivating of the receiver; and

operating said power application circuitry for activating fast oscillator of said clock prior to said step of enabling the phase adjustment capability of the DPLL.

20. A system for operating a radiotelephone at reduced power, the radiotelephone comprising:

a receiver for receiving a sequence of messages of a control channel, each message having a synchronization portion and a data portion which follows the synchronization portion, the data portion comprising a plurality of data channels each of which has a succession of repeated data segments;

signal processing circuitry including synchronization circuitry responsive to the synchronization portion of an individual one of said messages to enable a reading of data of the data portion of an individual one of said messages, said signal processing circuitry including a digital phase locked loop (DPLL) with phase adjustment capability, said signal processing circuitry applying electric power to said DPLL continuously from a steady source of power, said DPLL being synchronized by a bit stream of a selected data segment of said data segments of an N^th message of said sequence of messages;

power application circuitry for application of electric power to said receiver;

reading means for accomplishing said reading of data, said reading means reading data of the selected data segment of said N^th message;

inhibiting means for inhibiting phase adjustment of the DPLL, and controller means for activating said inhibiting means subsequent to a reading of data by said reading means;

wherein said power application circuitry is operative for deactivating the receiver upon a conclusion of a reading of data of said selected data segment of said N^th message;

said power application circuitry is operative for activating the receiver subsequent to said N^th message at a predetermined time interval prior to occurrence of the selected data segment of an (N+1)^th message of said sequence of messages, said predetermined time interval being limited in duration to the duration of a transient settling time of the receiver upon an activation of the receiver; and

said controller means disables said inhibiting means for enabling the phase adjustment capability of the DPLL in an interval of time beginning at or prior to and continuing during the occurrence of the selected data segment of the (N+1)^th message.

21. A system according to claim 20 wherein the signal processing circuitry includes a clock for driving various components of the signal processing circuitry, the clock comprising a first relatively fast oscillator outputting a signal at a first frequency and being powered by said power application circuitry, a relatively slow oscillator outputting a signal at a second frequency lower than said first frequency and being powered by a steady source of power, frequency generation circuitry driven by the slow oscillator for outputting at least a further signal at a third frequency lower than said second frequency, the frequency generation circuitry including a selector for selecting the fast oscillator signal in place of the slow oscillator signal;

wherein said power application circuitry is operative to deactivate said fast oscillator of said clock substantially concurrently with said deactivating of the receiver; and

said power application circuitry is operative for activating said fast oscillator of said clock prior to an enabling of the phase adjustment capability of said DPLL.