Method for fabricating reliable metallization with Ta-Si-N barrier for semiconductors

• US 5,614,437 A
• Filed: 01/26/1995
• Issued: 03/25/1997
• Est. Priority Date: 01/26/1995
• Status: Expired due to Term

• Current Assignee: Bell Semiconductor, LLC (Hilco Inc. (d/b/a Hilco Global))
• Original Assignee: LSI Logic Corporation (Broadcom, Inc.)
• Inventors: Choudhury, Ratan K.
• Primary Examiner(s): Bowers, Jr., Charles L.
• Assistant Examiner(s): GURLEY, LYNNE ANN
• Application Number:
  US08/378,750
• Time in Patent Office: 789 Days
• Field of Search: 437/190, 437/52, 437/200, 437/192, 437/194, 437/195, 437/197
• US Class Current: 438/653
• CPC Class Codes: H01L 21/76843 formed in openings in a dielectric
• CPC Class Codes: H01L 21/76846 Layer combinations
• CPC Class Codes: H01L 23/53223 Additional layers associated with aluminium layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 29/45 Ohmic electrodes
• CPC Class Codes: H01L 29/456 on silicon
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A method for manufacturing an ohmic contact on a semiconductor device, as disclosed herein, includes a first step of etching a via through a non-conductive layer formed over a partially fabricated version of the semiconductor device. This step exposes a region of a device element such as a source, gate electrode, etc. Next, an ohmic contact layer including tantalum and silicon is deposited over the partially fabricated device and in the vias by sputtering in an argon atmosphere. Thereafter, and in the same processing apparatus, a barrier layer including a tantalum silicon nitride is deposited over the ohmic contact layer. Then an aluminum alloy metallization layer is directly deposited on the partially fabricated device at a temperature of at least 650° C. At this deposition temperature, the metallization layer conformally fills the via, thereby producing a stable, uniform contact.

Claims

1. A method for manufacturing a semiconductor device, said semiconductor device including a silicon substrate having at least one device element and a non-conductive layer at least partially covering said device element, said method comprising the steps of:

etching a via extending through said non-conductive layer to said device element thereby providing an exposed region of said device element;

depositing a tantalum silicide ohmic contact layer over at least a first portion of said non-conductive layer and said via, said ohmic contact layer being in electrical contact with said exposed region;

depositing a tantalum silicon nitride barrier layer over at least a second portion of said non-conductive layer and said via, said barrier layer being in direct contact with said ohmic contact layer, and being in electrical contact with said exposed region; and

depositing a metallization layer upon said semiconductor device, said metallization layer formed over and in electrical contact with said exposed region, and wherein said metallization layer is aluminum or an aluminum containing alloy.

2. A method as recited in claim 1 wherein the step of depositing a metallization layer is performed at a temperature of at least about 650°

C.

3. A method as recited in claim 1 wherein said step of depositing a metallization layer is performed under conditions such that said metallization layer has a planar upper surface.

4. A method as recited in claim 1 further comprising the step of depositing an anti-reflective layer formed over said metallization layer.

5. A method as recited in claim 1 further comprising the step of depositing a wetting layer upon said semiconductor device, said wetting layer formed over and in electrical contact with said exposed region whereby said wetting layer provides a surface that is relatively easily wettable by aluminum.

6. A method as recited in claim 5 further comprising the step of depositing a metallization layer upon said semiconductor device, said metallization layer formed over and in electrical contact with said exposed region.

7. A method as recited in claim 6 further comprising the step of depositing an anti-reflective layer on said metallization layer.

8. A method as recited in claim 1 wherein the step of etching is performed by a plasma etching method.

9. A method as recited in claim 1 wherein the step of etching is performed with diluted HF.

10. A method as recited in claim 1 wherein the deposition of said ohmic contact layer is performed by reactive sputtering of a tantalum-silicon target in an Ar plasma.

11. A method as recited in claim 10 wherein the deposition of said barrier layer is performed by reactive sputtering of the tantalum-silicon target in a N₂ /Ar plasma.

12. A method for manufacturing a semiconductor device, said semiconductor device including a silicon substrate having at least one device element and a non-conductive layer at least partially covering said device element, said method comprising the steps of:

etching a via extending through said non-conductive layer to said device element thereby providing an exposed region of said device element;

depositing a tantalum silicide ohmic contact layer over at least a first portion of said non-conductive layer and said via, said ohmic contact layer being in electrical contact with said exposed region;

depositing tantalum silicon nitride barrier layer over at least a second portion of said non-conductive layer and said via, said barrier layer being in direct contact with said ohmic contact layer, and being in electrical contact with said exposed region; and

depositing a metallization layer on top of said tantalum silicon nitride barrier layer, whereby said tantalum silicon nitride layer acts as a barrier to transport of atoms from said metallization layer to said silicon substrate, and wherein said metallization layer is aluminum, or an aluminum containing alloy.

13. A method as recited in claim 12 wherein the step of depositing a metallization layer is performed at a temperature of at least about 650°

C.

14. A method as recited in claim 12 wherein said step of depositing a metallization layer is performed under conditions such that said metallization layer has a planar upper surface.

15. A method as recited in claim 12 further comprising the step of depositing an anti-reflective layer formed over said metallization layer.

16. A method as recited in claim 12 further comprising the step of depositing a wetting layer upon said semiconductor device, said wetting layer formed over and in electrical contact with said exposed region whereby said wetting layer provides a surface that is relatively easily wettable by the metallization layer.

17. A method as recited in claim 12 wherein the deposition of said ohmic contact layer is performed by reactive sputtering of a tantalum-silicon target in an Ar plasma.

18. A method as recited in claim 17 wherein the deposition of said barrier layer is performed by adding nitrogen to the argon plasma after the ohmic contact layer has been formed whereby tantalum silicon nitride is deposited on said ohmic contact layer.

19. A method as recited in claim 12 wherein the deposition of said barrier layer is performed by reactive sputtering of a tantalum-silicon target in a N₂ /Ar plasma.