CMOS-PECL level conversion circuit

• US 5,614,843 A
• Filed: 01/05/1996
• Issued: 03/25/1997
• Est. Priority Date: 01/09/1995
• Status: Expired due to Fees

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Mita, Shinji, Kuroda, Tadahiro
• Primary Examiner(s): Hudspeth, David R.
• Application Number:
  US08/583,510
• Time in Patent Office: 445 Days
• Field of Search: 326/33-34, 326/68, 326/69, 326/73, 326/115
• US Class Current: 326/73
• CPC Class Codes: H03K 19/018528 with at least one differential stage

Abstract

A level conversion circuit is provided which can obtain a stable output voltage, with keeping low power consumption and a high speed operation, if manufacturing processes and operational conditions of the LSI'"'"'S are varied. The level conversion circuit comprising a first input portion for receiving a first CMOS level signal as a differential signal at the CMOS level and a second CMOS level signal as an inverted signal of the first CMOS level signal, and outputting a first output current and a second output current based on these signals, a first conversion output portion for outputting a first PECL level signal as the PECL level differential signal and a second PECL level signal as an inverted signal of the first PECL level signal based on the first output current and the second output current from the first input portion, and a first current control portion for controlling the first output current and the second output current in the first conversion output portion by a first current control signal and a second current control signal so as to determine high level and low level in the first PECL level signal and the second PECL level signal.

Claims

1. A level conversion circuit for converting CMOS level differential signals into PECL level differential signals, comprising:

a first input portion for receiving a first CMOS level signal as a differential signal at said CMOS level and a second CMOS level signal formed as an inverted signal of said first CMOS level signal, and outputting a first output current and a second output current based on these signals;

a first conversion output portion for outputting a first PECL level signal as said PECL level differential signal and a second PECL level signal as an inverted signal of said first PECL level signal based on said first output current and said second output current from said first input portion; and

a first current control portion for controlling said first output current and said second output current in said first conversion output portion by a first current control signal and a second current control signal so as to determine a high level and a low level in said first PECL level signal and said second PECL level signal.

2. A level conversion circuit as claimed in claim 1, further comprising:

a second input portion, a second conversion output portion, and a second current control portion, all being formed to have respectively the same configurations as those of said first input portion, said first conversion output portion, and said first current control portion;

a first signal generating means for generating a first feedback signal based on a third PECL level signal output from said second conversion output portion;

a second signal generating means for generating a second feedback signal based on a fourth PECL level signal output as an inverted signal of said third PECL level signal from said second conversion output portion; and

a replica bias circuit formed to feed back said first feedback signal and said second feedback signal to said second current control portion, and to employ an input signal supplied to said second input portion as a first power source and a second power source;

wherein said first feedback signal and said second feedback signal output from said replica bias circuit may serve respectively as said first current control signal and said second current control signal.

3. A level conversion circuit comprising:

a first switching transistor and a second switching transistor connected respectively between a first node and a common node and a second node and said common node, for effecting ON/OFF operations alternately based on a first CMOS level signal serving as a CMOS level differential signal and a second CMOS level signal formed as an inverted signal of said first CMOS level signal;

a first conversion output portion for outputting a first PECL level signal of PECL level differential signals to a first output node depending upon a current flowing through said first node;

a second conversion output portion for outputting a second PECL level signal formed as an inverted signal of said first PECL level signal to a second output node depending upon a current flowing through said second node;

a first current control transistor for controlling a current to flow through said common node based on a first current control signal;

a second current control transistor for controlling a current to flow through said first node based on a second current control signal; and

a third current control transistor for controlling a current to flow through said second node based on said second current control signal.

4. A level conversion circuit as claimed in claim 3, further comprising:

a third switching transistor and a fourth switching transistor, a fourth current control transistor through a sixth current control transistor, and a third conversion output portion and a fourth conversion output portion, all being formed to have respectively the same configurations as those of said first switching transistor and said second switching transistor, said first current control transistor through said third current control transistor, and said first conversion output portion and said second conversion output portion;

a first signal generating means for generating a first feedback signal based on a third PECL level signal output from said third conversion output portion to a third output node;

a second signal generating means for generating a second feedback signal based on a fourth PECL level signal output as an inverted signal of said third PECL level signal from said fourth conversion output portion to a fourth output node; and

a replica bias circuit formed to feed back said first feedback signal to a control electrode of said fourth current control transistor and said second feedback signal to control electrodes of said fifth current control transistor and said sixth current control transistor, and to connect respectively a first power source and a second power source to respective control electrodes of said third switching transistor and said fourth switching transistor;

wherein said first feedback signal output from said replica bias circuit is supplied as said first current control signal to a control electrode of said first current control transistor, and said second feedback signal is supplied respectively as said second current control signal to respective control electrodes of said second current control transistor and said third current control transistor.

5. A level conversion circuit as claimed in claim 4, further comprising:

a first low power consumption transistor connected between said first power source and said first output node, conduction of said first low power consumption transistor being controlled based on said second CMOS level signal; and

a second low power consumption transistor connected between said first power source and said second output node, conduction of said second low power consumption transistor being controlled based on said first CMOS level signal;

wherein said replica bias circuit comprises;

a third low power consumption transistor connected between said first power source and said third output node and formed to have the same configuration as that of said first low power consumption transistor, a control electrode of said third low power consumption transistor being connected to said second power source; and

a fourth low power consumption transistor connected between said first power source and said fourth output node and formed to have the same configuration as that of said second low power consumption transistor, a control electrode of said fourth low power consumption transistor being connected to said first power source.

6. A level conversion circuit as claimed in claim 5, wherein control electrodes of said first low power consumption transistor through said fourth low power consumption transistor are connected to said second power source.

7. A level conversion circuit for receiving CMOS level differential signals from a first input terminal and a second input terminal and converting said CMOS level differential signals into PECL level differential signals to output from a first output terminal and a second output terminal, comprising:

a first CMOS inverter connected between a first power source and a common node, for receiving one of said CMOS level differential signals as an input signal;

a first current mirror circuit having an input current terminal connected to an output terminal of said first CMOS inverter and an output current terminal connected to said first output terminal;

a second CMOS inverter connected between said first power source and said common node, for receiving the other of said CMOS level differential signals as an input signal;

a second current mirror circuit having an input current terminal connected to an output terminal of said second CMOS inverter and an output current terminal connected to said second output terminal;

a first current control transistor connected between said common node and a second power source, for controlling a current flowing through said common node based on a first current control signal;

a first output transistor connected between said first power source and said first output terminal, conduction of said first output transistor being controlled based on a first current control signal; and

a second output transistor connected between said first power source and said second output terminal, conduction of said second output transistor being controlled based on a second current control signal.

8. A physical layer controller for an ATM communication control apparatus comprising:

a signal transfer processing section for receiving transmission data from upper data link layers and converting said transmission data into pulse trains at a CMOS level to output them at predetermined transfer rate; and

a CMOS-PECL level conversion circuit for converting said pulse trains at said CMOS level from said signal transfer processing section into pulse trains at a PECL level to output them as differential signals;

wherein said CMOS-PECL level conversion circuit comprises;

a first input portion for receiving a first CMOS level signal as said differential signals at said CMOS level and a second CMOS level signal formed as an inverted signal of said first CMOS level signal and outputting a first current and a second current based on said first CMOS level signal and said second CMOS level signal;

a first conversion output portion for outputting a first PECL level signal formed as said PECL level differential signals and a second PECL level signal formed as an inverted signal of said first PECL level signal based on a first output current and a second output current from said first input portion; and

a first current control portion for controlling a first output current and a second output current from said first conversion output portion by a first current control signal and a second current control signal to determine a high level and a low level of said first PECL level signal and said second PECL level signal respectively.