Delay-locked loop

• US 5,614,855 A
• Filed: 08/21/1995
• Issued: 03/25/1997
• Est. Priority Date: 02/15/1994
• Status: Expired due to Fees

• Current Assignee: Rambus Inc.
• Original Assignee: Rambus Inc.
• Inventors: Lee, Thomas H., Johnson, Mark G., Donnelly, Kevin S., Ho, Tsyr-Chyang
• Primary Examiner(s): Callahan, Timothy P.
• Assistant Examiner(s): Shin, Eunja
• Application Number:
  US08/512,597
• Time in Patent Office: 582 Days
• Field of Search: 327/141, 327/144, 327/145-150, 327/152, 327/153, 327/154-159, 327/161, 327/162, 327/231, 327/233, 327/234, 327/235, 327/236, 327/243, 327/244, 327/250, 327/175 , 327/176, 327/276, 331/17
• US Class Current: 327/158
• CPC Class Codes: H03L 7/0816 the controlled phase shifter and the frequency- or phase-detection arrangement being connected to a common input

Abstract

A delay locked loop (DLL) is described in which a phase detector compares the phase of the output of the DLL with that of a reference input. The output of the phase comparator drives a differential charge pump which functions to integrate the phase comparator output signal over time. The charge pump output controls a phase shifter with unlimited range that adjusts the phase of the DLL output so that the output of the phase comparator is high 50% of the time on average. Because the DLL adjusts the phase shifter until the output of the phase detector is high 50% of the time, on average, the relationship of the DLL output clock to the input reference clock depends only on the type of phase detector used. For example, when a data receiver is used as the phase detector in the DLL, the output of the DLL is a clock signal which can be used as a sampling clock for data receivers elsewhere in the system, and is timed to sample data at the optional instant independent of temperature, supply voltage and process variations. Alternatively, a quadrature phase detector may be employed to generate a clock signal that possesses a quadrature (90° ) relationship with a reference clock signal input. This may be used, for example, to generate a transmit clock for a data transmission device. Furthermore, the DLL is controlled to minimize dither jitter while minimizing acquisition time. In addition, duty cycle correcting amplifiers are employed to produce a DLL output clock that has a desired duty cycle, for example 50%. Additionally, the inputs to the charge pump are reversed in alternate quadrants of the phase plane in order to enable unlimited phase shift with a finite control voltage range.

Claims

1. A circuit for generating an output signal in a predetermined timing relationship with an input signal, comprising:

a duty cycle correcting amplifier coupled to receive the input signal, said amplifier correcting the duty cycle of the input signal to a predetermined duty cycle to produce a duty cycle corrected input signal;

a phase detector coupled to receive the input signal and the output signal, said phase detector generating an output signal indicative of whether the output signal is ahead or behind the input signal in phase;

a charge pump coupled to receive the output of the phase detector, said charge pump generating an output current; and

a phase shifter coupled to receive the duty cycle corrected input signal, the output signal from the phase detector and the output current from the charge pump, said phase shifter performing a phase shift of the duty cycle corrected input signal to produce the output signal, said phase shifter driven by the output current of the charge pump, said direction of the phase shift indicated by the phase detector;

wherein the phase of the output signal dithers around the phase of the input signal such that the output of the phase detector is a signal of a first state 50% of the time, on average.

2. A circuit for generating an output signal in a predetermined timing relationship with an input signal, comprising:

a phase detector coupled to receive the input signal and the output signal, said phase detector generating an output signal indicative of whether the output signal is ahead or behind the input signal in phase;

a charge pump coupled to receive the output of the phase detector, said charge pump generating an output current;

a boost control signal coupled to the charge pump, said signal indicating when the circuit is in an acquisition mode wherein the circuit functions to acquire the desired timing relationship between the input signal and the output signal, said charge pump generating greater output current when said boost control signal is in a first state indicative that the circuit is in the acquisition mode;

a phase shifter coupled to receive the input signal, the output signal from the phase detector and the output current from the charge pump, said phase shifter performing a phase shift of the input signal to produce the output signal, said phase shifter driven by the output current of the charge pump, said direction of the phase shift indicated by the phase detector;

wherein the jitter in the circuit is minimized by increasing the current output by the charge pump when the circuit is in the acquisition mode and maintaining the current output at a lower level when the circuit is not in the acquisition mode.

3. A method for generating an output signal having a predetermined timing relationship with an input signal, said method comprising the steps of:

correcting the duty cycle of the input signal to a predetermined duty cycle to produce a duty cycle corrected input signal;

generating a phase output signal indicative of whether the output signal is ahead or behind the input signal in phase;

generating a current; and

performing a phase shift of the duty cycle corrected input signal to produce the output signal, said step driven by the current, said direction of the phase shift indicated by the phase detector;

wherein the phase of the output signal dithers around the phase of the input signal such that the output of the phase detector is a signal of a first state 50% of the time, on average.