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Delay-locked loop

  • US 5,614,855 A
  • Filed: 08/21/1995
  • Issued: 03/25/1997
  • Est. Priority Date: 02/15/1994
  • Status: Expired due to Fees
First Claim
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1. A circuit for generating an output signal in a predetermined timing relationship with an input signal, comprising:

  • a duty cycle correcting amplifier coupled to receive the input signal, said amplifier correcting the duty cycle of the input signal to a predetermined duty cycle to produce a duty cycle corrected input signal;

    a phase detector coupled to receive the input signal and the output signal, said phase detector generating an output signal indicative of whether the output signal is ahead or behind the input signal in phase;

    a charge pump coupled to receive the output of the phase detector, said charge pump generating an output current; and

    a phase shifter coupled to receive the duty cycle corrected input signal, the output signal from the phase detector and the output current from the charge pump, said phase shifter performing a phase shift of the duty cycle corrected input signal to produce the output signal, said phase shifter driven by the output current of the charge pump, said direction of the phase shift indicated by the phase detector;

    wherein the phase of the output signal dithers around the phase of the input signal such that the output of the phase detector is a signal of a first state 50% of the time, on average.

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