N-phase modulated signal demodulation system with carrier reproduction

• US 5,614,861 A
• Filed: 09/12/1995
• Issued: 03/25/1997
• Est. Priority Date: 05/18/1995
• Status: Expired due to Fees

• Current Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Original Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Inventors: Harada, Hiroyuki
• Primary Examiner(s): Grimm, Siegfried H.
• Application Number:
  US08/527,043
• Time in Patent Office: 560 Days
• Field of Search: 329/304, 329/307, 329/308, 329/309, 329/310, 375/324, 375/325, 375/326, 375/327, 375/328, 375/329, 375/332
• US Class Current: 329/308
• CPC Class Codes: H04L 27/2272 using phase locked loops H04L27/2273 takes precedence

Abstract

A phase modulated signal demodulation system which is not affected by noise and distortion of an input signal. The system includes a carrier reproduction PLL circuit for generating a reproduction reference clock having a frequency which is N times of a carrier frequency which is synchronized with an N-phase phase modulated input signal, and a clock generation circuit for dividing the reproduction reference clock by 1/N and for generating N clocks, each of which has a different phase offset by 360°/N. The system further includes a phase detector which detects a phase of the N-phase phase modulated signal by using the N clocks together with the input N-phase phase modulated signal; and an operating circuit which detects a data edge of the input signal and the reproduction reference clock. The system further includes a data clock reproduction PLL circuit for generating a clock synchronized with a data rate using an output from the operating circuit, and a second clock generation circuit which generates a plurality of clocks for majority judgments using an output of the data clock reproduction PLL circuit. The system further includes a data protection circuit for protecting data generated by the phase detector, and a data generating circuit which outputs a corresponding digital data according to phase information outputted from the phase detector.

Claims

1. An N-phase phase modulated signal demodulation system comprising:

a carrier reproduction PLL circuit for generating a reproduction reference clock having a frequency which is N times that of a carrier frequency which is synchronized with an N-phase phase modulated signal inputted from an input terminal;

a clock generation circuit for dividing said reproduction reference clock by 1/N and for generating N clocks, each of which has different phase offset by 360°

/N;

a phase detector which detects a phase of said N-phase phase modulated signal by using said N clocks obtained from said clock generation circuit together with an input of said N-phase phase modulated signal; and

a data generating circuit which outputs corresponding digital data according to the phase detected by said phase detector.

3. A phase modulated signal demodulation system of claim 1, wherein said data generating circuit generates a demodulation code corresponding to any one of N detection output levels.

7. A phase modulated signal demodulation system of claim 1, wherein said phase detector further comprises a series of detection banks each corresponding to one of said N clocks, and each detection bank comprising:

an exclusive OR gate,

a comparing register, and

a logical gate;

said exclusive OR gate carrying out an exclusive OR operation between an input of said N-phase phase modulated signal and a respective one of said N clocks to produce an output applied to a respective comparing register, and said comparing register producing an output applied to said logical gate to determine the phase of said N-phase phase modulated signal relative to the respective one of said clocks.

9. A phase modulated signal demodulation system of claim 7, wherein each said comparing register comprises a cascade connection of a plurality of D flip-flops;

a first of said cascaded plurality of D flip-flops having an input to which is applied the output of the respective exclusive OR gate and which is propagated throughout said cascaded plurality of D flip-flops in synchronization with said reproduction reference clock to the output of said comparing register.

2. A phase modulated signal demodulation system comprising:

a carrier reproduction PLL circuit for generating a reproduction reference clock having a frequency which is N times that of a carrier frequency which is synchronized with an N-phase phase modulated signal inputted from an input terminal;

a clock generation circuit for dividing said reproduction reference clock by 1/N and for generating N clocks, each of which has different phase offset by 360°

/N;

a phase detector which detects a phase of said N-phase phase modulated signal by using said N clocks obtained from said clock generation circuit together with an input of said N-phase phase modulated signal;

an operating circuit which detects data edges of said N-phase phase modulated signal using said reproduction reference clock;

a data clock reproduction PLL circuit for generating a clock synchronized with said data edges of said N-phase phase modulated signal using an output from said operating circuit;

a second clock generation circuit which generates a plurality of clocks using an output of said data clock reproduction PLL circuit;

a data protection circuit for protecting phase information of said N-phase phase modulated signal output from said phase detector; and

a data generating circuit which outputs corresponding digital data according to phase information of said N-phase phase modulated signals protected by said data protection circuit.

4. A phase modulated signal demodulation system of claim 2, wherein said data generating circuit generates a demodulation code corresponding to any one of N detection output levels.

5. A phase modulated signal demodulation system of claim 2, wherein said N-phase phase modulated signal is a QPSK input signal, and said operating circuit comprises a phase shifter of 45°

and a phase detector for multiplying said QPSK input signal with a signal having a phase advanced by 45°

from a reference clock.

6. A phase modulated signal demodulation system of claim 2, wherein said N-phase phase modulated signal is a QPSK input signal, and said operating circuit further comprises:

a phase shifter producing signals advanced by 45° and

lagging by 45°

relative to a reference clock; and

a phase detector multiplying said QPSK input signal by signals produced from said phase shifter.

8. A phase modulated signal demodulation system of claim 2, wherein said phase detector further comprises a series of detection banks each corresponding to one of said N clocks, and each detection bank comprising:

an exclusive OR gate,

a comparing register, and

a logical gate;

said exclusive OR gate carrying out an exclusive OR operation between an input of said N-phase phase modulated signal and a respective one of said N clocks to produce an output applied to a respective comparing register, and said comparing register producing an output applied to said logical gate to determine the phase of said N-phase phase modulated signal relative to the respective one of said clocks.

10. A phase modulated signal demodulation system of claim 8, wherein each said comparing register comprises a cascade connection of a plurality of D flip-flops;

a first of said cascaded plurality of D flip-flops having an input to which is applied the output of the respective exclusive OR gate and which is propagated throughout said cascaded plurality of D flip-flops in synchronization with said reproduction reference clock to the output of said comparing register.

11. A phase modulated signal demodulation system of claim 2, comprising:

said second clock generation circuit producing signals α

, γ

, β

;

said phase detector further comprising a plurality of outputs;

said data protection circuit having a series of data count arrays, one said data count array for each of said phase detector outputs;

each said data count array comprising a NAND gate, a cascade connection of T flip-flops, and a D flip-flop;

each NAND gate having as inputs said signal α and

a respective output of said phase detector, and having an output applied to said cascade connection of T flip-flops;

said cascade connection of T flip-flops forming a majority counter, said majority counter outputting a majority value of said phase detector output in synchronization with signal α

;

said cascaded T flip-flops having an output input into said D flip-flop in synchronization with said signal β

;

said cascaded T flip-flops being reset in synchronization with said signal γ

;

each said D flip-flop corresponding to each said data count array forming said phase information of said N-phase phase modulated signals.

12. A phase modulated signal demodulation system of claim 4, comprising:

said second clock generation circuit producing signals α

, γ

, β

;

said phase detector further comprising a plurality of outputs;

said data protection circuit having a series of data count arrays, one said data count array for each of said phase detector outputs;

each said data count array comprising a NAND gate, a cascade connection of T flip-flops, and a D flip-flop;

each NAND gate having as inputs said signal α and

a respective output of said phase detector, and having an output applied to said cascade connection of T flip-flops;

said cascade connection of T flip-flops forming a majority counter, said majority counter outputting a majority value of said phase detector output in synchronization with signal α

;

said cascaded T flip-flops having an output input into said D flip-flop in synchronization with said signal β

;

said cascaded T flip-flops being reset in synchronization with said signal γ

;

each said D flip-flop corresponding to each said data count array forming said phase information of said N-phase phase modulated signals.

13. A phase modulated signal demodulation system of claim 6, comprising:

said second clock generation circuit producing signals α

, γ

, β

;

said phase detector further comprising a plurality of outputs;

said data protection circuit having a series of data count arrays, one said data count array for each of said phase detector outputs;

each said data count array comprising a NAND gate, a cascade connection of T flip-flops, and a D flip-flop;

each NAND gate having as inputs said signal α and

a respective output of said phase detector, and having an output applied to said cascade connection of T flip-flops;

said cascade connection of T flip-flops forming a majority counter, said majority counter outputting a majority value of said phase detector output in synchronization with signal α

;

said cascaded T flip-flops having an output input into said D flip-flop in synchronization with said signal β

;

said cascaded T flip-flops being reset in synchronization with said signal γ

;

each said D flip-flop corresponding to each said data count array forming said phase information of said N-phase phase modulated signals.

14. A phase modulated signal demodulation system of claim 5, comprising:

said second clock generation circuit producing signals α

, γ

, β

;

said phase detector further comprising a plurality of outputs;

said data protection circuit having a series of data count arrays, one said data count array for each said phase detector outputs;

each said data count array comprising a NAND gate, a cascade connection of T flip-flops, and a D flip-flop;

each NAND gate having as inputs said signal α and

a respective output of said phase detector, and having an output applied to said cascade connection of T flip-flops;

said cascade connection of T flip-flops forming a majority counter, said majority counter outputting a majority value of said phase detector output in synchronization with signal α

;

said cascaded T flip-flops having an output input into said D flip-flop in synchronization with said signal β

;

said cascaded T flip-flops being reset in synchronization with said signal γ

;

each said D flip-flop corresponding to each said data count array forming said phase information of said N-phase phase modulated signals.

15. A phase modulated signal demodulation system of claim 8, comprising:

said second clock generation circuit producing signals α

, γ

, β

;

said phase detector further comprising a plurality of outputs;

said data protection circuit having a series of data count arrays, one said data count array for each of said phase detector outputs;

each said data count array comprising a NAND gate, a cascade connection of T flip-flops, and a D flip-flop;

each NAND gate having as inputs said signal α and

a respective output of said phase detector, and having an output applied to said cascade connection of T flip-flops;

said cascade connection of T flip-flops forming a majority counter, said majority counter outputting a majority value of said phase detector output in synchronization with signal α

;

said cascaded T flip-flops having an output input into said D flip-flop in synchronization with said signal β

;

said cascaded T flip-flops being reset in synchronization with said signal γ

;

each said D flip-flop corresponding to each said data count array forming said phase information of said N-phase phase modulated signals.

16. A phase modulated signal demodulation system of claim 10, comprising:

said second clock generation circuit producing signals α

, γ

, β

;

said phase detector further comprising a plurality of outputs;

said data protection circuit having a series of data count arrays, one said data count array for each of said phase detector outputs;

each said data count array comprising a NAND gate, a cascade connection of T flip-flops, and a D flip-flop;

each NAND gate having as inputs said signal α and

a respective output of said phase detector, and having an output applied to said cascade connection of T flip-flops;

said cascade connection of T flip-flops forming a majority counter, said majority counter outputting a majority value of said phase detector output in synchronization with signal α

;

said cascaded T flip-flops having an output input into said D flip-flop in synchronization with said signal β

;

said cascaded T flip-flops being reset in synchronization with said signal γ

;

each said D flip-flop corresponding to each said data count array forming said phase information of said N-phase phase modulated signals.