Event driven interface having a dynamically reconfigurable counter for monitoring a high speed data network according to changing traffic events

• US 5,615,135 A
• Filed: 06/01/1995
• Issued: 03/25/1997
• Est. Priority Date: 06/01/1995
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Waclawsky, John G., Hershey, Paul C.
• Primary Examiner(s): Cosimano, Edward R.
• Application Number:
  US08/456,759
• Time in Patent Office: 663 Days
• Field of Search: 364/514 B, 364/550, 364/551.01, 395/180, 395/184.01
• US Class Current: 702/182
• CPC Class Codes: G06F 11/348 Circuit details, i.e. tracer hardware
• CPC Class Codes: G06F 2201/86 Event-based monitoring
• CPC Class Codes: G06F 2201/88 Monitoring involving counting
• CPC Class Codes: H04L 43/00 Arrangements for monitoring or testing data switching networks
• CPC Class Codes: H04L 43/12 Network monitoring probes

Abstract

A hardwired, dynamically reconfigurable counter array counts occurrences of different traffic events having different rates of occurrences monitored on a high speed data network by an Event Driven Interface (EDI). The array includes a plurality of "N" bit counters, where "N" is a binary multiple. The counters are arranged in an array of size "m,n", where "m" is the number of rows and "n" is the number of columns in the array. A signal input is provided to each counter as a first input, each signal being definitive of a specific traffic event occurring on the high speed network. Each counter is connected to the adjacent counter in the column through a multi-terminal logic element, each logic element in a column receives the output of a counter as a first input and provides an output to the succeeding counter as a second input. A counter logic switch responsive to an input signal generates a counter logic vector as an output. The vector comprises a plurality of outputs, each output being provided to a different row of the array as a second input to each logic element. Means are provided for changing the signal inputs and/or the counter logic vector to configure or reconfigure the counters in the array to individual or group counters of the same or different sizes. The counter sizes are selected to match the counting requirements of different traffic events being monitored on the network by the EDI.

Claims

1. In an event driven interface (EDI) for a high speed data communications network, a hardwired, dynamically reconfigurable counter array for counting the occurrences of different traffic events having different rates of occurrences being monitored on the network by the EDI, comprising:

a) a plurality of "N" bit counters, where "N" is a binary multiple;

the counters being arranged in an array of size "m,n", where "m" is the number of rows and "n" is the number of columns in the array;

(b) a signal input to each counter as a first input, each signal being definitive of a specific traffic event occurring on the high speed network;

(c) each counter connected to the adjacent counter in the column through a multi-terminal logic element;

each logic element in a column receiving the output of counter as a first input and providing an output to the succeeding counter as a second input;

(d) a control vector C(i) definitive of the signal inputs to be counted by the respective counters;

(e) a counter logic switch responsive to a counter logic vector for providing a plurality of outputs, each output provided to a different row of the array as a second input to each logic element in the same row of the array; and

(f) means for changing the contents of the control vector C(i) and/or the counter logic vector to configure or re-configure the counters in the array to individual or group counters of the same or different sizes for matching the counting requirements of different traffic events being monitored on the network by the EDI to such individual or groups of counters.

2. The counter array of claim 1 wherein the counters provide outputs of different counter sizes according to the control vector c(i) and/or the counter logic vector.

3. The counter array of claim 2 wherein the logic element is a multiplexer.

4. The counter array of claim 3 wherein the counter is a standard binary counter.

5. The counter array of claim 4 wherein the counter outputs are multiples of the standard binary counter.

6. The counter array of claim 5 wherein the outputs of the counters are combined into an event vector E(i) for use by an expert system.

7. The counter array of claim 6 further wherein the array is reconfigured in real time without altering the timing or the frequency of occurrences of the traffic events being monitored on the network by the EDI.

8. In an event driven interface (EDI) for a high speed data communications network, a hardwired, dynamically reconfigurable counter array for counting the occurrences of different traffic events having different rates of occurrences being monitored on the network by the EDI, a method of configuring or reconfiguring the counter array comprising the steps of:

a) identifying the traffic events to be monitored by the EDI and counted by the array;

b) forming and providing a control vector C(i) as an input to the EDI for specifying the traffic events to be monitored by the EDI and counted by the array;

c) calculating the frequency of occurrences of the different traffic events being monitored by the EDI;

d) determining a counter logic vector for application to the array to configure or re-configure the array into individual or groups of counters for matching the counting requirement of the traffic events to the size of the counter or groups of counters for counting such traffic events; and

e) applying the counter logic vector to a counter logic switch for configuring or re-configuring the array to count in real time the occurrences of different traffic events having different rates of occurrences being monitored on the network by the EDI without altering the timing of such traffic events on the network.

9. The method of claim 8 further comprising the step of forming an event vector E(i) from the array outputs for use by an expert system in controlling the performance of the network.

10. The method of claim 9 wherein the counter logic vector forms the array to provide a plurality of outputs corresponding to the number of counters, each output being a different binary multiple.

11. The method of claim 10 wherein the counter logic vector in combination with the control vector C(i) form the array to provide a plurality of outputs less than the number of counters in the array and of different or the same binary multiple.