Digital bus simulator integrated in a system for automatically testing electronic packages embarked on an aircraft

• US 5,615,136 A
• Filed: 11/21/1994
• Issued: 03/25/1997
• Est. Priority Date: 11/22/1993
• Status: Expired due to Term

• Current Assignee: Airbus Operations SAS (Airbus SE)
• Original Assignee: Aerospatiale Societe Nationale Industrielle
• Inventors: Rieusse, Jean-Pierre, Sulmont, Benjamin, Baraton, Jean-Yves
• Primary Examiner(s): Teska, Kevin J.
• Assistant Examiner(s): LOPPNOW, MATTHEW CLAY
• Application Number:
  US08/342,828
• Time in Patent Office: 855 Days
• Field of Search: 395/282, 395/283, 364/578
• US Class Current: 703/21
• CPC Class Codes: G06F 11/261 by simulating additional hardware, e.g. fault simulation
• CPC Class Codes: G06F 30/15 Vehicle, aircraft or watercraft design
• CPC Class Codes: G06F 30/331 with hardware acceleration, e.g. by using field programmable gate array [FPGA] or emulation

Abstract

The present invention relates to an integrated digital bus simulator system for automatically testing electronic packages embarked on an aircraft including a computer. This bus simulator is able to reconfigured under the control of the computer of the system by reconfigurating its hardware and software so as to simulate the digital buses used on the aircraft. The system includes a bus simulation module which is reconfigurable in accordance with the bus to be simulated and with the wired logic downloaded into this module so as to adapt the architecture of the hardware to the purpose of the bus to be simulated.

Claims

1. Digital bus simulator integrated in a test system for automatically testing electronic devices embarked on a suitable aircraft so as to simulate the digital buses used on the aircraft, which is reconfigured under the control of a computer for the test system by reconfiguring the test system software and hardware, this reconfiguration being required so as to be adapted to digital interface, coding, protocol and the speed requirements specific to each simulated digital bus, and the architecture of which is able to download into the latter the applicative software and the wired logic of the automata able to simulate a new digital bus;

comprising;

at least a first and second processor, at least a first and second memory bank and reconfigurable logic circuits, wherein

the first processor ensures communication with the computer for the test system by observing the communication protocols,

the second processor ensures management of the buses used by executing the applicative software to be downloaded into said first memory for each simulated digital bus;

with the second memory bank being accessible by the second processor and with the logic required to control this memory bank being implemented in a reconfigurable logic circuit;

a bus interface module embodying the hardware interfacing for each digital bus on said aircraft and for receiving signals from said bus;

the first processor being integrated in this module;

a central processing unit communications module comprising the circuits for authorizing exchanges of information between said first and second processor and with a controller for said bus, with the second processor being integrated in this module;

an application central processing unit for carrying out the configuration and operational functions of each digital bus to be simulated;

a bus simulation module which autonomously carries out exchange of information on the simulated bus, with said simulation module being reconfigurable according to the bus to be simulated with wired logic automata downloaded into this module so as to adapt the architecture of the hardware to the purpose of the bus to be simulated; and

an analog interface module embodying the analog material adaptation for the simulated bus for delivering simulated bus signals.

2. Simulator according to claim 1 and appearing in the form of a single instrument.

3. Simulator according to claim 2 wherein the single instrument comprises an electronic card.

4. Simulator according to claim 3, wherein wired logic automata required to carry out bus simulation are downloaded into volatile-memory configurable circuits.

5. Simulator according to claim 1, wherein the central processing unit communications module comprises:

a VXI shared memory;

a double port shared memory;

an asynchronous events module;

a "watchdog" module;

a control register,

this module containing the hardware elements allowing for the exchange of information between the VXI bus, the VXI interface module and the application central processing unit.

6. Simulator according to claim 1, wherein the application central processing unit includes:

a central processing unit;

a local working memory;

a programmable variable clock module;

a module for processing exceptions;

a system clock module and various ports;

a hardware triggering signal management module connected to the first and second buses,

one output of this central processing unit being connected to the central processing unit communications module and another output being connected to the bus application simulation module, this application central processing unit providing the material resources required for exploiting the bus simulators, as well as the bus processor which ensures the exploitation of the simulated buses.

7. Simulator according to claim 1, wherein the digital bus simulation module comprises all the hardware required to autonomously carry out exchanges of information on the simulated buses and includes:

a bus isolation module, LCA bus decoding, and simulator registers;

A DMA controller and dating clock module;

a reconfigurable bus simulation module;

an exchange memory;

a data bus translator module;

specialized peripheral units;

line adaptation circuits;

the inputs and outputs of this module being connected respectively to the application central processing unit, the second bus of the material triggering signals and to the analog interface card, the final output delivering the simulated bus signals.