Non-volatile ferroelectric memory device with leakage preventing function

• US 5,615,144 A
• Filed: 08/04/1995
• Issued: 03/25/1997
• Est. Priority Date: 08/12/1994
• Status: Expired due to Fees

• Current Assignee: NEC Electronics Corporation (Renesas Electronics Corporation)
• Original Assignee: NEC Corporation
• Inventors: Kimura, Tohru, Koike, Hiroki
• Primary Examiner(s): Nguyen, Viet Q.
• Application Number:
  US08/511,527
• Time in Patent Office: 599 Days
• Field of Search: 365/145, 365/117, 365/189.09
• US Class Current: 365/145
• CPC Class Codes: G11C 11/22 using ferroelectric elements

Abstract

A non-volatile ferroelectric memory device includes a plurality of memory cells provided in a matrix manner, each of which comprises a transistor having a gate and source and drain regions formed in a semiconductor region, and a ferroelectric capacitor having first and second electrodes and a ferroelectric layer interposed between the first and second electrodes. The second electrode is connected to one of the source and drain regions of the transistor. The memory device further includes a plurality of pairs of bit lines, each of the bit lines of each of the pairs being connected to the other of the source and drain regions of the transistor of each memory cell in a column of the plurality of memory cells, a plurality of word lines each of which is connected to the gate of the transistor of each memory cell in a row of the plurality of memory cells, a plate potential section for generating a first predetermined potential intermediate between a reference potential and a high DC voltage and supplying the first potential to the first electrode of each of the plurality of memory cells, a well potential section for generating a second predetermined potential lower than the first potential with respect to the reference potential and supplying the second potential to the semiconductor region of each of the plurality of transistors, and a sense amplifier section for sensing a data using potentials on the bit lines of each of the plurality of pairs of bit lines. The well potential section functions as a preventing section for preventing a leakage current from flowing from the ferroelectric layer.

Claims

1. A non-volatile ferroelectric memory device comprising:

a plurality of memory cells provided in a matrix manner, each of which comprises a transistor having a gate and source and drain regions formed in a semiconductor region, and a ferroelectric capacitor having first and second electrodes and a ferroelectric layer interposed between said first and second electrodes, said second electrode being connected to one of said source and drain regions of said transistor;

a plurality of pairs of bit lines, each of said bit lines of each of said pairs being connected to the other of said source and drain regions of said transistor of each memory cell in a column of said plurality of memory cells;

a plurality of word lines each of which is connected to said gate of said transistor of each memory cell in a row of said plurality of memory cells;

plate potential means for generating a first predetermined potential intermediate between a reference potential and a high DC voltage and supplying said first potential to said first electrode of each of said plurality of capacitors;

well potential means for generating a second predetermined potential lower than said first potential with respect to the reference potential and supplying said second potential to the semiconductor region of each of said plurality of transistors; and

sense amplifier means for sensing a data using potentials on the bit lines of each of said plurality of pairs of bit lines.

2. The non-volatile ferroelectric memory device according to claim 1, wherein said plate potential means generates said first potential in a range of (the high DC voltage--a threshold voltage of the transistor)/2 to (the high voltage)/2.

3. The non-volatile ferroelectric memory device according to claim 1, wherein said well potential means generates said second potential such that a potential difference between said first potential and said second potential is smaller than a coercive voltage of said ferroelectric layer.

4. The non-volatile ferroelectric memory device according to claim 1, wherein said well potential means generates said second potential such that said second potential is smaller than a potential corresponding to a turn-on voltage of a diode formed by said semiconductor region and one of said source and drain regions.

5. The non-volatile ferroelectric memory device according to claim 3, wherein said well potential means generates said second potential such that said second potential is smaller than a potential corresponding to a turn-on voltage of a diode formed by said semiconductor region and one of said source and drain regions.

6. The non-volatile ferroelectric memory device according to claim 1, wherein said first and second potentials have predetermined fixed values, respectively.

7. The non-volatile ferroelectric memory device according to claim 1, wherein a potential of each of said plurality of word lines is equal to or lower than said second potential when said each word line is not selected.

8. The non-volatile ferroelectric memory device according to claim 1, said plate potential means and said well potential means generates said first and second potentials from a single DC voltage supplied to the memory device.

9. The non-volatile ferroelectric memory device according to claim 1, wherein said first and second potentials are both equal to each other when said DC voltage is not applied and said first and second potentials have a relative relationship such that a potential difference between the first and second potentials is smaller than a coercive voltage when said DC voltage is applied.

10. In a non-volatile ferroelectric memory device comprising a plurality of memory cells provided in a matrix manner, each of which comprises a transistor having a gate and source and drain regions formed in a semiconductor region, and a ferroelectric capacitor having first and second electrodes and a ferroelectric layer interposed between said first and second electrodes, said second electrode being connected to one of said source and drain regions of said transistor, a method of operating the memory device with less leakage current from a memory cell, comprising the steps of:

generating a first predetermined fixed potential intermediate between a reference potential and a high DC voltage to supply said first potential to the second electrode of the memory cell;

generating a second predetermined fixed potential lower than said first potential with respect to the reference potential to supply said second potential to the semiconductor region of the transistors; and

sensing a data of the memory cell using potentials on a bit line connected to the memory cell when the memory cell is selected.

11. The method according to claim 10, wherein said step of generating a second potential includes generating said second potential such that a potential difference between said first potential and said second potential is smaller than a coercive voltage of said ferroelectric layer.

12. The method according to claim 10, wherein said step of generating a second potential includes generating said second potential such that said second potential is smaller than a potential corresponding to a turn-on voltage of a diode formed by said semiconductor region and one of said source and drain regions.

13. The method according to claim 10, wherein a potential of a word line connected to the gate of the transistor is equal to or lower than said second potential when said memory cell is not selected.

14. The method according to claim 10, said first and second potentials are generated from a single DC voltage supplied to the memory device.

15. The method according to claim 14, wherein said first and second potentials are both equal to each other when said DC voltage is not applied and said first and second potentials have a relative relationship such that a potential difference between the first and second potentials is smaller than a coercive voltage when said DC voltage is applied.

16. A non-volatile ferroelectric memory device comprising:

a plurality of memory cells provided in a matrix manner, each of which comprises a transistor having a gate and source and drain regions formed in a semiconductor region, and a ferroelectric capacitor having first and second electrodes and a ferroelectric layer interposed between said first and second electrodes, said second electrode being connected to one of said source and drain regions of said transistor;

a plurality of pairs of bit lines, each of said bit lines of each of said pairs being connected to the other of said source and drain regions of said transistor of each memory cell in a column of said plurality of memory cells;

a plurality of word lines each of which is connected to said gate of said transistor of each memory cell in a row of said plurality of memory cells;

plate potential means for generating a predetermined plate potential intermediate between a reference potential and a high DC voltage and supplying said plate potential to said first electrode of each of said plurality of memory cells;

sense amplifier means for sensing a data using potentials on the bit lines of each of said plurality of pairs of bit lines; and

preventing means for preventing a leakage current from flowing from said ferroelectric layer.

17. The non-volatile ferroelectric memory device according to claim 16, wherein said preventing means generates a semiconductor region potential such that said semiconductor region potential is smaller than a potential corresponding to a turn-on voltage of a diode formed by said semiconductor region and said one of said source and drain regions and supplies the generated potential to said semiconductor region.

18. The non-volatile ferroelectric memory device according to claim 16, wherein said preventing means generates a semiconductor region potential such that said semiconductor region potential is higher than a potential of each of said plurality of word lines when said each word line is not selected.

19. The non-volatile ferroelectric memory device according to claim 16, wherein said preventing means includes well potential means for generating a predetermined semiconductor region potential lower than said plate potential with respect to the reference potential and supplying said semiconductor region potential to the semiconductor region of each of said plurality of transistors.

20. The non-volatile ferroelectric memory device according to claim 19, wherein said well potential means generates said second potential such that a potential difference between said plate potential and said semiconductor region potential is smaller than a coercive voltage of said ferroelectric layer.

21. A semiconductor memory device comprising:

a plurality of memory cells each having a transistor and storage capacitor coupled together;

a plate potential circuit for generating a first predetermined potential to an electrode of a plurality of said storage capacitors; and

a well potential circuit for generating a second predetermined potential lower than said first predetermined potential to a well region of said transistors.

22. The semiconductor memory device according to claim 21, wherein said first predetermined potential is intermediate between a reference potential and a high DC voltage and said second predetermined potential is lower than said first predetermined potential with respect to said reference potential.

23. The semiconductor memory device according to claim 22, wherein said plate potential circuit generates said second predetermined potential in a range of (the high DC voltage--a threshold voltage of the transistor)/2 to (the high DC voltage)/2.

24. The semiconductor memory device according to claim 21, wherein said well potential circuit generates said second predetermined potential such that a potential difference between said first predetermined potential and said second predetermined potential is smaller than a coercive voltage of a dielectric layer of said storage capacitors.

25. The semiconductor memory device according to claim 21, wherein said well potential circuit generates said second predetermined potential such that said second predetermined potential is smaller than a potential corresponding to a turn-on voltage of a diode formed by a semiconductor region of said transistors and one of a source and a drain regions of said transistors.

26. In a semiconductor memory device comprising a plurality of memory cells each having a transistor coupled to a storage capacitor which has electrodes and a dielectric layer interposed between said electrodes, a method of operating the memory device with less leakage current from a memory cell, comprising the steps of:

generating a first predetermined potential intermediate between a reference potential and a high DC voltage to supply said first predetermined potential to one of said electrodes of the storage capacitors; and

generating a second predetermined potential lower than said first predetermined potential with respect to the reference potential to supply said second predetermined potential to a semiconductor region of said transistors.

27. The method according to claim 26, wherein said step of generating a second predetermined potential includes generating said second predetermined potential such that a potential difference between said first predetermined potential and said second predetermined potential is smaller than a coercive voltage of said dielectric layer.

28. The method according to claim 26, wherein said step of generating a second predetermined potential includes generating said second predetermined potential such that said second predetermined potential is smaller than a potential corresponding to a turn-on voltage of a diode formed by said semiconductor region and one of a source and a drain region of said transistors.