Semiconductor memory device

• US 5,615,163 A
• Filed: 02/08/1996
• Issued: 03/25/1997
• Est. Priority Date: 12/21/1993
• Status: Expired due to Term

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Masuoka, Fujio, Tanaka, Tomoharu, Nakamura, Hiroshi, Hasegawa, Takehiro, Momodomi, Masaki, Sakui, Koji
• Primary Examiner(s): Fears, Terrell W.
• Application Number:
  US08/598,706
• Time in Patent Office: 411 Days
• Field of Search: 365/182, 365/189.01, 365/189.04, 365/230.01, 365/230.03, 365/235
• US Class Current: 365/230.03
• CPC Class Codes: G11C 16/0416 comprising cells containing a single floating gate transistor and no select transistor, e.g. UV EPROM
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: G11C 29/80 with improved layout
• CPC Class Codes: G11C 5/025 Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device geometrical lay-out of the components in integrated circuits, H01L27/0207

Abstract

An NAND cell type EEPROM comprising a memory cell array wherein an NAND cell unit having a plurality of electrically rewritable memory cells is connected in series, and the NAND cell is formed on a semiconductor substrate in a matrix array, a plurality of control gate lines CG each provided to cross an NAND cell group of the same row, bit lines BL each provided to cross the NAND cell group of the same column, wherein driver circuit are provided at both sides of the memory cell array in a ratio of one to two NAND cell units so as to drive the control gate lines CG, the plurality of the control gate lines CG, provided to cross the NAND cell unit of the even row, is connected to the left driver circuit, and the plurality of the control gate lines CG, provided to cross the NAND cell unit of the odd row, is connected to the right driver circuit.

Claims

1. A semiconductor memory device comprising:

a memory cell array comprising a plurality of memory cell units arranged in a matrix form, each memory cell unit having a plurality of memory cells connected to one another;

a plurality of word-line drivers which are arranged in two rows, said word-line drivers, except at least one located at ends of rows, being divided into groups each including two word-line drivers, said groups of two word-line drivers and at least one word-line driver located at ends of rows being provided alternatively on a first and a second side of said memory cell array;

word lines for selecting said memory cells when driven by said word-line drivers, said word-lines being divided into word-line blocks each connected at a first end to one memory cell unit and at a second end to one word-line driver;

bit lines for writing and reading data to and from said memory cells;

row selecting means for selecting said word lines; and

column selecting means for selecting said bit lines;

wherein said word-line blocks are arranged in a row, said word-line blocks, except at least one located at ends of the row, are divided into groups of two word-line blocks and the two word-line blocks of each group are connected to the two word-line drivers of one group, respectively.

2. The semiconductor memory device according to claim 1, wherein said memory cell unit is formed by connecting said plurality of said memory cells in series.

3. The semiconductor memory device according to claim 1, wherein said memory cell unit is formed by connecting said plurality of memory cells in parallel.

4. The semiconductor memory device according to claim 1, wherein only one of the driver circuits provided at a right and left of the memory cell array is selected to be operated during data erasing and writing.

5. The semiconductor memory device according to claim 1, wherein the row selecting means is provided at both sides of said memory cell array to correspond to said word-line driver.

6. The semiconductor memory device according to claim 1, further comprising:

a spare memory cell array for saving a defective cell of said memory cell array;

a plurality of spare word line drivers arranged at both sides of said spare memory cell array; and

a defect saving circuit for storing an address of a defective cell to select said spare word line driver in a case where an inputted address coincides with the address of the defective cell.

7. The semiconductor memory device according to claim 5, further comprising a signal line for supplying an output signal sent from said row selecting means to said word-line driver, wherein said signal line does not cross said memory cell array.

8. The semiconductor memory device according to claim 6, wherein said memory cell unit is formed by connecting said plurality of said memory cells in series.

9. The semiconductor memory device according to claim 5, wherein said memory cell unit is formed by connecting said plurality of memory cells in parallel.

10. The semiconductor memory device according to claim 6, wherein only one of the driver circuits provided at a right and left of the memory cell array is selected to be operated during data erasing and writing.

11. The semiconductor memory device according to claim 6, wherein the row selecting means is provided at both sides of said memory cell array to correspond to said word-line driver.

12. The semiconductor memory device according to claim 10, further comprising a signal line for supplying an output signal sent from said row selecting means to said word-line driver, wherein said signal line does not cross said memory cell array.