PCMCIA SRAM card function using DRAM technology
First Claim
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1. An apparatus for a computer system having a PCMCIA interface, said apparatus comprising:
- a DRAM device for providing a plurality of memory locations for said computer system;
an SRAM to DRAM logic interface for receiving a series of PCMCIA SRAM control signals and access information transmitted by said computer system across said PCMCIA interface, said PCMCIA SRAM control signals and access information being associated with said plurality of memory locations provided by said DRAM device, and for converting said series of PCMCIA SRAM control signals to a series of DRAM control signals, and for directing said series of DRAM control signals and said access information to said DRAM device for providing a compatible communication link between said computer system and said DRAM device across said PCMCIA interface, said DRAM to SRAM logic further including means for refreshing said DRAM device and for arbitrating between said refreshing of said DRAM device and said providing of said compatible communication link between said computer system and said DRAM device; and
a PCMCIA detector removably coupled to said PCMCIA interface for receiving a supply voltage provided by the computer system across the PCMCIA interface for said DRAM device, and for detecting and providing a power down indication output signal when said supply voltage provided by the computer system across the PCMCIA interface falls below a predetermined voltage level, and for detecting and providing a power up indication output signal when said supply voltage rises above said predetermined voltage level;
and wherein said SRAM to DRAM logic interface is removably coupled to the PCMCIA interface for receiving the series of PCMCIA SRAM control signals and access information from the computer system, and said SRAM to DRAM logic interface is coupled to said PCMCIA detector for receiving said power down indication output signal from said PCMCIA detector and for responding to said power down indication output signal from said PCMCIA detector by causing all pending communication, if any, between the computer system and the DRAM device to complete, and then quiescing the PCMCIA interface, and then forcing the DRAM device into a data-retention mode, and for receiving said power up indication output signal form said PCMCIA detector and for responding to said power up indication output signal by forcing said DRAM out of said data-retention mode.
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Abstract
An apparatus may be used with a computer system having a PCMCIA interface. The apparatus employs a DRAM device and logic for converting the PCMCIA SRAM control signals into DRAM control signals, so as to permit the communication of data and control signals between the computer system and the DRAM device. The apparatus further provides controls for refreshing the DRAM device, and for arbitrating between the functions of refreshing the DRAM and providing for communication between the DRAM and the computer system. The apparatus further provides the power management functions required for operating a DRAM device in a PCMCIA environment.
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Citations
11 Claims
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1. An apparatus for a computer system having a PCMCIA interface, said apparatus comprising:
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a DRAM device for providing a plurality of memory locations for said computer system; an SRAM to DRAM logic interface for receiving a series of PCMCIA SRAM control signals and access information transmitted by said computer system across said PCMCIA interface, said PCMCIA SRAM control signals and access information being associated with said plurality of memory locations provided by said DRAM device, and for converting said series of PCMCIA SRAM control signals to a series of DRAM control signals, and for directing said series of DRAM control signals and said access information to said DRAM device for providing a compatible communication link between said computer system and said DRAM device across said PCMCIA interface, said DRAM to SRAM logic further including means for refreshing said DRAM device and for arbitrating between said refreshing of said DRAM device and said providing of said compatible communication link between said computer system and said DRAM device; and a PCMCIA detector removably coupled to said PCMCIA interface for receiving a supply voltage provided by the computer system across the PCMCIA interface for said DRAM device, and for detecting and providing a power down indication output signal when said supply voltage provided by the computer system across the PCMCIA interface falls below a predetermined voltage level, and for detecting and providing a power up indication output signal when said supply voltage rises above said predetermined voltage level; and wherein said SRAM to DRAM logic interface is removably coupled to the PCMCIA interface for receiving the series of PCMCIA SRAM control signals and access information from the computer system, and said SRAM to DRAM logic interface is coupled to said PCMCIA detector for receiving said power down indication output signal from said PCMCIA detector and for responding to said power down indication output signal from said PCMCIA detector by causing all pending communication, if any, between the computer system and the DRAM device to complete, and then quiescing the PCMCIA interface, and then forcing the DRAM device into a data-retention mode, and for receiving said power up indication output signal form said PCMCIA detector and for responding to said power up indication output signal by forcing said DRAM out of said data-retention mode. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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Specification