PCMCIA SRAM card function using DRAM technology

• US 5,615,328 A
• Filed: 08/30/1995
• Issued: 03/25/1997
• Est. Priority Date: 08/30/1995
• Status: Expired due to Fees

• Current Assignee: Lenovo Singapore Pte Limited (Lenovo Group Ltd.)
• Original Assignee: International Business Machines Corporation
• Inventors: White, Kraig R., Hadderman, Scott J.
• Primary Examiner(s): Beausoliel, Jr., Robert W.
• Assistant Examiner(s): Snyder, Glenn
• Application Number:
  US08/521,509
• Time in Patent Office: 573 Days
• Field of Search: 395/182.2, 365/222
• US Class Current: 714/22
• CPC Class Codes: G06F 13/1694 Configuration of memory controller to different memory types

Abstract

An apparatus may be used with a computer system having a PCMCIA interface. The apparatus employs a DRAM device and logic for converting the PCMCIA SRAM control signals into DRAM control signals, so as to permit the communication of data and control signals between the computer system and the DRAM device. The apparatus further provides controls for refreshing the DRAM device, and for arbitrating between the functions of refreshing the DRAM and providing for communication between the DRAM and the computer system. The apparatus further provides the power management functions required for operating a DRAM device in a PCMCIA environment.

Claims

1. An apparatus for a computer system having a PCMCIA interface, said apparatus comprising:

a DRAM device for providing a plurality of memory locations for said computer system;

an SRAM to DRAM logic interface for receiving a series of PCMCIA SRAM control signals and access information transmitted by said computer system across said PCMCIA interface, said PCMCIA SRAM control signals and access information being associated with said plurality of memory locations provided by said DRAM device, and for converting said series of PCMCIA SRAM control signals to a series of DRAM control signals, and for directing said series of DRAM control signals and said access information to said DRAM device for providing a compatible communication link between said computer system and said DRAM device across said PCMCIA interface, said DRAM to SRAM logic further including means for refreshing said DRAM device and for arbitrating between said refreshing of said DRAM device and said providing of said compatible communication link between said computer system and said DRAM device; and

a PCMCIA detector removably coupled to said PCMCIA interface for receiving a supply voltage provided by the computer system across the PCMCIA interface for said DRAM device, and for detecting and providing a power down indication output signal when said supply voltage provided by the computer system across the PCMCIA interface falls below a predetermined voltage level, and for detecting and providing a power up indication output signal when said supply voltage rises above said predetermined voltage level;

and wherein said SRAM to DRAM logic interface is removably coupled to the PCMCIA interface for receiving the series of PCMCIA SRAM control signals and access information from the computer system, and said SRAM to DRAM logic interface is coupled to said PCMCIA detector for receiving said power down indication output signal from said PCMCIA detector and for responding to said power down indication output signal from said PCMCIA detector by causing all pending communication, if any, between the computer system and the DRAM device to complete, and then quiescing the PCMCIA interface, and then forcing the DRAM device into a data-retention mode, and for receiving said power up indication output signal form said PCMCIA detector and for responding to said power up indication output signal by forcing said DRAM out of said data-retention mode.

2. The apparatus according to claim 1 wherein the SRAM to DRAM logic interface further includes:

an SRAM request interface for detecting when said series of PCMCIA SRAM control signals and said access information transmitted by said computer system across said PCMCIA interface, are associated with said plurality of memory locations provided by said DRAM device, and for receiving said series of PCMCIA SRAM control signals and said access information associated with said plurality of memory locations, said SRAM request interface coupled to an arbiter for sending an indication to said arbiter that said series of PCMCIA SRAM control signals and said access information have been detected;

said arbiter for receiving said indication from said SRAM request interface, said arbiter being coupled to a DRAM controller for sending a communication of the receipt of said indication from said SRAM request interface to said DRAM controller;

said DRAM controller for receiving said communication from said arbiter, said DRAM controller coupled to said DRAM device for converting said communication from said arbiter into said series of DRAM control signals, and for directing said series of DRAM control signals to said DRAM device, said DRAM controller further coupled to said SRAM request interface for directing said access information from said SRAM request interface to said DRAM device.

3. The apparatus according to claim 2 wherein said DRAM controller further determines when said DRAM device needs to be refreshed, and refreshes said DRAM device, and wherein said arbiter further detects when said DRAM controller will refresh said DRAM device and suspends the processing of said indication sent by said SRAM request interface when said indication has been received by said arbiter after said arbiter has detected that said DRAM controller will refresh said DRAM device, and wherein said arbiter will suspend the refreshing of said DRAM device by said DRAM controller when said indication from said SRAM request interface has been received by said arbiter before said arbiter has detected that said DRAM controller will refresh said DRAM device.

4. The apparatus according to claim 2 wherein said DRAM controller is coupled to said PCMCIA detector for receiving said power down indication output signal and for responding to said power down indication output signal by completing all pending communication, if any, between the computer system and the DRAM device, and for forcing the DRAM device into said data-retention mode, and for receiving said power up indication output signal from said PCMCIA detector, and for responding to said power up indication output signal by forcing the DRAM device out of said data-retention mode,

and wherein said SRAM request interface is coupled to said PCMCIA detector for receiving said power down indication output signal and for responding to said power down indication output signal by quiescing said PCMCIA interface.

5. The apparatus according to claim 1 wherein a power manager is coupled to the PCMCIA detector for receiving said power down indication output signal from said PCMCIA detector, and for responding to said power down indication output signal by switching the source of voltage provided to the DRAM device from the computer system to a power source independently operable from said computer system by coupling to said independently operable power supply, and for receiving said power up indication output signal from said PCMCIA detector, and for responding to said power up indication output signal by switching the source of voltage provided to the DRAM device from said independently operable power source to the computer system.

6. The apparatus according to claim 5 wherein said DRAM device is capable of operating at a first voltage level when said DRAM device is not in said data-retention mode, and operating at a second voltage level, lower than said first voltage level, when said DRAM device is in said data-retention mode.

7. The apparatus according to claim 6 wherein said power manager directs voltage to said DRAM device at said first voltage level until said DRAM device has been forced into said data-retention mode, and directs voltage to said DRAM device at said second voltage level after said DRAM device has been forced into said data-retention mode.

8. The apparatus according to claim 5 wherein said power manager is coupled to said SRAM to DRAM logic interface and wherein said power manager further directs the supply voltage from the computer system to said SRAM to DRAM logic interface until said SRAM to DRAM logic interface has forced the DRAM device into said data-retention mode.

9. The apparatus according to claim 5 wherein the power manager is removably coupled to said PCMCIA interface for receiving said supply voltage from said computer system.

10. The apparatus according to claim 5 wherein the power manager is further coupled to said PCMCIA detector for receiving said supply voltage from said computer system via said PCMCIA detector.

11. The apparatus according to claim 1 wherein said predetermined voltage level is the lower limit of a PCMCIA safe voltage level allowed for the operation of said PCMCIA interface.